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參數(shù)資料
| 型號(hào)： | ADM1487EARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX HALF DUP RS485/422 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RS422，RS485 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
ADM485E/ADM487E/ADM1487E
Rev. B | Page 5 of 16
VCC = 5 V ± 10%, TA = TMIN to TMAX, unless otherwise noted.
Table 4. ADM487E
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Driver Propagation Delay Input to Output, Low to High
tDPLH
250
800
2000
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see
Driver Propagation Delay Input to Output, High to Low
tDPHL
250
800
2000
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see
Output Skew to Output
tSKEW
250
20
800
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see
Rise/Fall Time
tDR, tDF
250
2000
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see
Enable Time to High Level
tDZH
250
2000
ns
CL = 100 pF, S1 closed (see
Enable Time to Low Level
tDZL
2000
ns
CL = 100 pF, S1 closed (see
Disable Time from Low Level
tDLZ
300
3000
ns
CL = 15 pF, S1 closed (see
Disable Time from High Level
tDHZ
300
3000
ns
CL = 15 pF, S1 closed (see
RECEIVER
Receiver Propagation Delay Input to Output, Low to High
tRPLH
250
2000
ns
See
Receiver Propagation Delay Input to Output, High to Low
tRPHL
250
2000
ns
See
|tPLH tPHL| Differential Receiver Skew
tSKEW
100
ns
See
Enable Time to Low Level
tRZL
25
50
ns
CL = 15 pF, S2 closed (see
Enable Time to High Level
tRZH
25
50
ns
CL = 15 pF, S1 closed (see
Disable Time from Low Level
tRLZ
25
50
ns
CL = 15 pF, S2 closed (see
Disable Time from High Level
tRHZ
25
50
ns
tPLH, tPHL < 50% of data period
Maximum Data Rate
fMAX
250
kbps
Time to Shutdown1
tSHDN
50
200
600
ns
Driver Enable from Shutdown to Output High
tDZH(SHDN)
5000
ns
CL = 100 pF, S1 closed (see
Driver Enable from Shutdown to Output Low
tDZL(SHDN)
5000
ns
CL = 100 pF, S1 closed (see
Receiver Enable from Shutdown to Output High
tRZH(SHDN)
5000
ns
CL = 15 pF, S2 closed (see
Receiver Enable from Shutdown to Output Low
tRZL(SHDN)
5000
ns
CL = 15 pF, S1 closed (see
1 The ADM487E is put into shutdown mode by bringing RE high and DE low. If the inputs are in this state for less than 50 ns, the parts are guaranteed not to enter
shutdown. If the inputs are in this state for at least 600 ns, the ADM487E is guaranteed to enter shutdown.
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