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參數(shù)資料
| 型號(hào)： | ADM1487EARZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 5 V, 【15 kV ESD Protected Half-Duplex, RS-485/RS-422 Transceivers |
| 中文描述： | LINE TRANSCEIVER, PDSO8 |
| 封裝： | ROHS COMPLIANT, MS-012AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 297K |
| 代理商： | ADM1487EARZ-REEL7 |
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ADM485E/ADM487E/ADM1487E
V
CC
= 5 V ± 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Rev. 0 | Page 5 of 16
Table 4. ADM487E
Parameter
DRIVER
Input to Output
Symbol
t
DPLH
Min
250
Typ
800
Max
2000
Unit
ns
Test Conditions/Comments
R
DIFF
= 54 Ω,
CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
R
DIFF
= 54 Ω,
CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
R
DIFF
= 54 Ω,
CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
R
DIFF
= 54 Ω,
CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
t
DPHL
250
800
2000
ns
Output Skew to Output
t
SKEW
250
20
800
ns
Rise/Fall Time
t
DR
, t
DF
250
2000
ns
Enable Time to High Level
Enable Time to Low Level
Disable Time from Low Level
Disable Time from High Level
RECEIVER
Input to Output
t
DZH
t
DZL
t
DLZ
t
DHZ
250
300
300
2000
2000
3000
3000
2000
2000
ns
ns
ns
ns
ns
ns
C
RL
= 100 pF, S2 closed (see Figure 21)
C
RL
= 100 pF, S1 closed (see Figure 22)
C
RL
= 15 pF, S1 closed (see Figure 22)
C
RL
= 15 pF, S2 closed (see Figure 21)
R
DIFF
= 54 Ω,
CL1 = CL2 = 100 pF
R
DIFF
= 54 Ω,
CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
C
RL
= 15 pF, S1 closed
(see Figure 23 and Figure 24)
C
RL
= 15 pF, S2 closed (see Figure 25)
C
RL
= 15 pF, S1 closed (see Figure 25)
C
RL
= 15 pF, S2 closed (see Figure 25)
t
PLH
, t
PHL
< 50% of data period
C
L
= 100 pF, S2 closed (see Figure 21)
C
L
= 100 pF, S1 closed (see Figure 22)
C
L
= 15 pF, S2 closed (see Figure 25)
C
L
= 15 pF, S1 closed (see Figure 25)
t
RPLH
t
RPHL
250
250
|t
PLH
t
PHL
| Differential Receiver Skew
t
SKEW
100
ns
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
Maximum Data Rate
Time to Shutdown
1
Driver Enable from Shutdown to Output High
Driver Enable from Shutdown to Output Low
Receiver Enable from Shutdown to Output High
t
RZL
t
RZL
t
RLZ
t
RHZ
f
MAX
t
DZH(SHDN)
t
DZL(SHDN)
t
RZL(SHDN)
t
RZH(SHDN)
250
50
25
25
25
25
200
5000
5000
5000
50
50
50
50
600
ns
ns
ns
ns
kbps
ns
ns
ns
ns
1
The ADM487E is put into shutdown mode by bringing the RE high and the DE low. If the inputs are in this state for less than 50 ns, the parts are guaranteed not to
enter shutdown. If the inputs are in this state for at least 600 ns, the ADM487E is guaranteed to enter shutdown.
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