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參數(shù)資料
| 型號(hào)： | ADM1487E |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 V, 【15 kV ESD Protected Half-Duplex, RS-485/RS-422 Transceivers |
| 中文描述： | 5，【15千伏ESD保護(hù)半V型雙工，RS-485/RS-422收發(fā)器 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 297K |
| 代理商： | ADM1487E |
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ADM485E/ADM487E/ADM1487E
TIMING SPECIFICATIONS
Rev. 0 | Page 4 of 16
V
CC
= 5 V ± 5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3. ADM485E/ADM1487E
Parameter
DRIVER
Input to Output
Symbol
t
DPLH
Min
10
Typ
40
Max
60
Unit
ns
Test Conditions/Comments
R
DIFF
= 54 Ω,
CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
R
DIFF
= 54 Ω,
CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
R
DIFF
= 54 Ω,
CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
R
DIFF
= 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
C
RL
= 100 pF, S2 closed (see Figure 21)
C
RL
= 100 pF, S1 closed (see Figure 22)
C
RL
= 15 pF, S1 closed (see Figure 22)
C
RL
= 15 pF, S2 closed (see Figure 21)
R
DIFF
= 54 Ω
,
CL1 = CL2 = 100 pF
(see Figure 23 and Figure 24)
R
DIFF
= 54 Ω
,
CL1 = CL2 = 100 pF
(see Figure 4 and Figure 5)
C
RL
= 15 pF, S2 closed (see Figure 25)
C
RL
= 15 pF, S1 closed (see Figure 25)
C
RL
= 15 pF, S2 closed (see Figure 25)
t
PLH
, t
PHL
< 50% of data period
t
DPHL
10
40
60
ns
Output Skew to Output
t
SKEW
5
10
ns
Rise/Fall Time
t
DR
, t
DF
3
20
40
ns
Enable Time to High Level
Enable Time to Low Level
Disable Time from Low Level
Disable Time from High Level
RECEIVER
Input to Output
t
DZH
t
DZL
t
DLZ
t
DHZ
t
RPLH
20
45
45
45
45
60
70
70
70
70
200
ns
ns
ns
ns
ns
|t
PLH
t
PHL
| Differential Receiver Skew
t
SKEW
5
ns
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
MAXIMUM DATA RATE
t
RZL
t
RZL
t
RLZ
t
RHZ
f
MAX
2.5
25
20
20
20
50
50
50
50
ns
ns
ns
ns
Mbps
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