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參數(shù)資料
| 型號(hào)： | ADM1232AARW |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | Microprocessor Supervisory Circuit |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大小： | 122K |
| 代理商： | ADM1232AARW |
ADM1232
–5–
REV. B
STROBE
T imeout Selection
T D or time delay set is used to set the Strobe T imeout Period.
T he Strobe T imeout Period is defined as being the maximum
time between high-to-low transitions (Figure 4) that
STROBE
will accept before a reset will be asserted. T he Strobe timeout
settings are listed in T able I.
T able I.
Condition
Min
T yp
Max
Units
T D = 0 V
T D = Floating
T D = V
CC
62.5
250
500
150
600
1200
250
1000
2000
ms
ms
ms
STROBE
TIMEOUT PERIOD
STROBE
STROBE
PULSE WIDTH
Figure 4.
STROBE
Parameters
V
CC
RESET
+5V
RESET
+4.5V (5% TRIP POINT)
RESET OUTPUT DELAY
WHEN IS V
CC
FALLING
RESET OUTPUT DELAY
WHEN IS V
CC
RISING
+5V
+4.25V (10% TRIP POINT)
Figure 5. Reset Output Delay
T OLE RANCE
T he T OLERANCE input is used to determine the level V
CC
can
vary below 5 V without the ADM1232 asserting a reset. Con-
necting T OLERANCE to ground will select a –5% tolerance
level and will cause the ADM1232 to generate a reset if V
CC
falls below 4.75 V (typical). If T OLERANCE is connected to
V
CC
a –10% tolerance level is selected and will cause the
ADM1232 to generate a reset if V
CC
falls below 4.5 V (typical).
Check the parameters for the V
CC
trip point in the ADM1232
Specifications for more information.
RE SE T AND
RESET
OUT PUT S
While RESET is capable of sourcing and sinking current,
RESET
is an open drain MOSFET which sinks current only.
T herefore, it is necessary to pull this output high.
CIRCUIT INFORMAT ION
PB RESET
T he
PB RESET
input makes it possible to manually reset a system
using either a standard push-button switch or a logic low
input. An internal debounce circuit provides glitch immunity
when used with a switch, reducing the effects of glitches on the
line. T he debounce circuit is guaranteed to cause the ADM1232
to assert a reset if
PB RESET
is brought low for more than 20 ms
and is guaranteed to ignore low inputs of less than 1 ms.
ADM1232
STROBE
RESET
TOLERANCE
STRESET
GND
TD
ADM1232
RESET
MICROPROCESSOR
I/O
V
CC
PB RESET
V
CC
Figure 2. Typical Push Button Reset Application
RESET
RESET
PB RESET
V
IL
V
IH
PB RESET TIME
RESET ACTIVE
TIME
PB RESET
DELAY
Figure 3.
PB RESET
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