參數(shù)資料
型號: ADM1064ASU
廠商: ANALOG DEVICES INC
元件分類: 電源管理
英文描述: Super Sequencer with Voltage Readback ADC
中文描述: 10-CHANNEL POWER SUPPLY SUPPORT CKT, QFP48
封裝: 7 X 7 MM, MS-026ABC, TQFP-48
文件頁數(shù): 18/32頁
文件大?。?/td> 523K
代理商: ADM1064ASU
ADM1064
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 24 shows how the simple building block of a
single SE state can be used to build a power-up sequence for a
3-supply system.
Rev. 0 | Page 18 of 32
Table 7 lists the PDO outputs for each state in the same SE
implementation. In this system, the presence of a good 5 V
supply on VP1 and the VX1 pin held low are the triggers
required for a power-up sequence to start. The sequence intends
to turn on the 3.3 V supply next, then the 2.5 V supply (assuming
successful turn-on of the 3.3 V supply). Once all three supplies
are good, the PWRGD state is entered, where the SE remains
until a fault occurs on one of the three supplies, or it is instructed
to go through a power-down sequence by VX1 going high.
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following sections, which describe the
individual blocks, use this sample application to demonstrate
the state machine’s actions.
0
IDLE1
IDLE2
EN3V3
DIS3V3
DIS2V5
PWRGD
FSEL1
FSEL2
SEQUENCE
STATES
MONITOR FAULT
STATES
TIMEOUT
STATES
VX1 = 0
VP1 = 1
VP1 = 0
(VP1 + VP2) = 0
(VP1 + VP2 + VP3) = 0
V(VP1 +
VP2 = 1
VP3 = 1
VP2 = 0
VX1 = 1
VP3 = 0
VP2 = 0
VP1 = 0
VX1 = 1
VX1 = 1
10ms
20ms
EN2V5
Figure 24. Sample Application Flow Diagram
Table 7. PDO Outputs for Each State
PDO Outputs
PDO1 = 3V3ON
PDO2 = 2V5ON
PDO3 = FAULT
IDLE1
0
0
0
IDLE2
0
0
0
EN3V3
1
0
0
EN2V5
1
1
0
DIS3V3
0
1
1
DIS2V5
1
0
1
PWRGD
1
1
0
FSEL1
1
1
1
FSEL2
1
1
1
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