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參數(shù)資料
| 型號： | ADL5500ACBZ-P2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 100 MHz to 6 GHz TruPwr Detector |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, BGA4 |
| 封裝： | ROHS COMPLIANT, WLCSP-4 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大小： | 1482K |
| 代理商： | ADL5500ACBZ-P2 |
ADL5500
INPUT COUPLING USING A SERIES RESISTOR
Figure 36 shows a technique for coupling the input signal into
the ADL5500 that can be applicable where the input signal is
much larger than the input range of the ADL5500. A series
resistor combines with the input impedance of the ADL5500 to
attenuate the input signal. Because this series resistor forms a
divider with the frequency dependent input impedance, the
apparent gain changes greatly with frequency. However, this
method has the advantage of very little power being tapped off
in RF power transmission applications. If the resistor is large
compared to the transmission line’s impedance, the VSWR of
the system is relatively unaffected.
Rev. A | Page 16 of 24
ADL5500
RFIN
RFIN
0
R
SERIES
Figure 36. Attenuating the Input Signal
MULTIPLE RF INPUTS
Figure 37 shows a technique for combining multiple RF input
signals to the ADL5500. Some applications can share a single
detector for multiple bands. Three 16.5 Ω resistors in a T-network
combine the three 50 Ω terminations (including the ADL5500).
The broadband resistive combiner ensures each port of the
T-network sees a 50 Ω termination. Because there is only 6 dB
of isolation from one port of the combiner to the other ports,
only one band should be active at a time.
ADL5500
RFIN
BAND 1
50
Ω
BAND 2
DIRECTIONAL
COUPLER
16.5
Ω
0
50
Ω
16.5
Ω
16.5
Ω
DIRECTIONAL
COUPLER
Figure 37. Combining Multiple RF Input Signals
SELECTING THE OUTPUT LOW-PASS FILTER
NETWORK
The ADL5500’s internal filter capacitor provides averaging in
the square domain but leaves some residual ac on the output.
Signals with high peak-to-average ratios, such as W-CDMA
or CDMA2000, can produce ac-residual levels on the ADL5500
dc output. To reduce the effects of these low frequency
components in the waveforms, some additional filtering is
required.
The output of the ADL5500 can be filtered by placing a
capacitor between VRMS (Pin 1) and ground. The combination
of the on-chip 1 kΩ output series resistance and the external
shunt capacitor forms a low-pass filter to reduce the residual ac.
Table 4 shows the effect of several capacitor values for various
communications standards with high peak-to-average ratios
along with the residual ripple at the output, in peak-to-peak and
rms volts. Note that large load capacitances increase the turn-on
and pulse response times (see Figure 29 and Figure 30).
Table 4. Waveform and Output Filter Effects on Residual AC
Output
Waveform
C
FILT
V dc
64QAM
0.01 μF
0.5
(7.4 dB CF)
1.0
2.0
0.1 μF
0.5
1.0
2.0
W-CDMA RL
0.01 μF
0.5
(3.4 dB CF)
1.0
2.0
0.1 μF
0.5
1.0
2.0
CDMA2000 UL
0.01 μF
0.5
(6.7 dB CF)
1.0
2.0
0.1 μF
0.5
1.0
2.0
Residual AC
mV p-p
7.0
7.4
7.6
6.7
7.2
7.4
10
16
45
7
9
14
46
85
191
17
31
68
mV rms
1.4
1.5
1.6
1.4
1.5
1.5
1.7
2.4
5.6
1.5
1.6
2.3
6
13
27
3
5
9
POWER CONSUMPTION AND POWER-ON/-OFF
RESPONSE
The quiescent current consumption of the ADL5500 varies with
the size of the input signal from approximately 1 mA for no
signal up to 6 mA at an input level of 0.7 V rms (10 dBm, re
50 Ω). If the input is driven beyond this point, the supply
current increases sharply (as shown in Figure 6). There is little
variation in quiescent current with power supply voltage.
The ADL5500 can be disabled by simply removing the power to
the device. Figure 32 shows a plot of the output response to the
supply being turned on (that is, VPOS is pulsed) with an output
shunt capacitor of 0.01 μF. Again, the turn-on time is influenced
strongly by the size of the output shunt capacitor.
To improve the falling edge of the supply gating response and
the pulse response, a resistor can be placed in parallel with the
output shunt capacitor. The added resistance helps discharge
the capacitor. Although this method reduces the power-off
time, the added load resistor also attenuates the output (see the
Output Drive Capability and Buffering section).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADL5500ACBZ-P7 | 100 MHz to 6 GHz TruPwr Detector |
| ADL5500-EVALZ | 100 MHz to 6 GHz TruPwr Detector |
| ADL5530 | DC to 1000 MHz IF Gain Block |
| ADL5530ACPZ-R7 | DC to 1000 MHz IF Gain Block |
| ADL5530ACPZ-WP | DC to 1000 MHz IF Gain Block |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADL5500ACBZ-P7 | 功能描述:IC DETECTOR RF/IF TRUPWR 4-WLCSP RoHS:是 類別:RF/IF 和 RFID >> RF 檢測器 系列:- 產(chǎn)品變化通告:Product Discontinuation 15/May/2006 標準包裝:3,000 系列:- 頻率:100MHz ~ 2GHz RF 型:手機，GSM，DCS，PCS 輸入范圍:- 精確度:- 電源電壓:2.7 V ~ 5.5 V 電流 - 電源:300µA 包裝:帶卷 (TR) 封裝/外殼:SC-74，SOT-457 其它名稱:NCS5000SNT1GOS |
| ADL5500-EVAL | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR ADL5500 IC POWER DETECTOR 制造商:Analog Devices 功能描述:EVAL BD FOR ADL5500 IC PWR DETECTOR - Bulk |
| ADL5500-EVALZ | 制造商:Analog Devices 功能描述:PWR DETECTOR - Bulk |
| ADL5501 | 制造商:AD 制造商全稱:Analog Devices 功能描述:50 MHz to 4 GHz TruPwr Detector |
| ADL5501_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:50 MHz to 6 GHz TruPwr Detector |
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