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參數(shù)資料
| 型號： | ADL5385 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 300 MHz to 1000 MHz Quadrature Modulator |
| 中文描述： | 300 MHz到1000 MHz的正交調制器 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 904K |
| 代理商： | ADL5385 |
ADL5370
SPECIFICATIONS
V
S
= 5 V; T
A
= 25°C; LO = 0 dBm
1
single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (f
BB
) = 1 MHz, unless otherwise noted.
Rev. 0 | Page 3 of 20
Table 1.
Parameter
ADL5370
Operating Frequency Range
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
Conditions
LO = 450 MHz
Range over which uncompensated sideband suppression < 30 dBc
Low frequency
High frequency
V
IQ
= 1.4 V p-p differential
P
OUT
(f
LO
+ (2 × f
BB
)), P
OUT
= 6.2 dBm
P
OUT
(f
LO
+ (3 × f
BB
)), P
OUT
= 6.2 dBm
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
= 2 dBm per tone
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
= 2 dBm per tone
I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset
6 MHz carrier offset, P
OUT
= 6 dBm, P
LO
= 6 dBm
Characterization performed at typical level
See
Figure 9
for a plot of return loss vs. frequency
Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN
Current sourcing from each baseband input with a bias of 500 mV dc
2
LO = 450 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc
LO = 450 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc
Pin VPS1 and Pin VPS2
Min
Typ
300
1000
6.2
11
50
41
0.76
0.03
65
54
60
24
160
Max
Unit
MHz
MHz
dBm
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
GSM
7
4.75
157
0
6
500
45
0.1
2900
70
350
205
+7
5.25
dBc/Hz
dBm
dB
mV
μA
μA
kΩ
MHz
MHz
V
mA
LO INPUTS
LO Drive Level
1
Input Return Loss
BASEBAND INPUTS
I and Q Input Bias Level
Input Bias Current
Input Offset Current
Differential Input Impedance
Bandwidth (0.1 dB)
Bandwidth (1 dB)
POWER SUPPLIES
Voltage
Supply Current
1
High LO drive reduces noise at a 6 MHz carrier offset in GSM applications.
2
See V-to-I converter discussion in the Circuit Description section for architecture information.
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