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參數(shù)資料
| 型號： | ADL5304ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP LOG CONV 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 對數(shù)轉(zhuǎn)換器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADL5304
Rev. 0 | Page 25 of 32
APPLICATIONS INFORMATION
USING THE ADL5304
The basic connections for single-supply operation are shown in
Figure 55. Supply decoupling is not critical and the suggested values
are conservative; however, it is recommended that a ferrite bead
be placed in the supply lines together with a 0.1 μF decoupling
capacitor. Ferrite beads are preferable to resistors because they do
not produce a dc voltage drop that can affect reference levels. In
Figure 55, the slope is 10 mV/dB or 0.2 V/decade, and the intercept
is 3.162 fA. For the full dynamic range of 200 dB (100 dB optical),
VLOG varies from 0.5 V to 2.5 V (see small diagram at the output
the IDEN pin is connected to the IREF pin, IDEN = 100 nA.
Figure 55 also shows the setup for the adaptive photodiode bias.
If this is not desired, ground the IMON pin, remove RMNTR, and
provide the desired bias voltage greater than 1.5 V to the cathode of
the PD. As noted in the Photodiode Bias section, the on-chip 2 V
reference can be used for this purpose and provides an exact 0.5 V
reverse bias together with the 1.5 V that is forced by the FET
amp to the anode via the INUM pin.
Using the Adaptive Bias
The positive bias on the photodiode cathode must be adequate
to support the peak current, which is limited by its internal series
resistance, RS. Typical values of RS are 5 Ω. A model of a repre-
sentative photodiode (JDSU EPM 605) is shown in Figure 54.
09
459
-06
3
PD
2
CASE
1
1nH
1.5nH
Rs
0.55pF
0.5pF
0.13pF
5nH
Figure 54. Photodiode Model
It is desirable to use a small bias at very low levels of
illumination to minimize the error due to current leakage
across the diode terminals. The adaptive bias achieves this
automatically even for larger currents through the addition
of the external resistor, RMNTR, that is 10 times RS. In case of
uncertainty in RS, an RMNTR that is slightly greater than 10 times
RS is recommended. In the limit, when RMNTR is not present at
all, the voltage at the IMON pin increases until the current
source saturates and absorbs the excess 10% of current that the
IMON output generates. However, this defeats the purpose of
the adaptive bias; therefore, users must ensure that RMNTR is
present when using the adaptive bias.
ADL5304
0
945
9-
06
4
2
30
3
4
5
8
7
MONITOR AND
PD BIAS
(1.1× INUM)
TEMPERATURE
COMPENSATION
32
31
26
9
IMON
VNUM INNM
VDEN
ACOM
COMM
INDN
1P5V
2VLT
DCBI
VPOS
BSDC
VSM1
1.5V
VSM2
1.5V
IREF
IDEN
INUM
VSM3
1.5V
VSM4
1.5V
10
11
27
29
100nA
1.5V
17
24
2V
BIAS AND
VREF
15
14
INPS
INMS
VLOG
23
22
5k
7.5k
21
20
19
18
SCL1
SCL2
SCL3
ACOM
RMNTR
6
PD
SHIELD
0.1F
HFCP
16
0.1F
1F
28
4.02
VNUM
VDEN
IMPORTANT: ~1mA
BIAS CURRENT FLOWS OUT
OF DCBI. NEEDS TO BE
CONNECTED TO 1P5V.
FB
VPOS
ILOG
RLOAD
2.5V
1.5V
0.5V
1p 100n 10m
NMFS VNEG DNFS
12
13
RNMFS
RDNFS
Figure 55. Basic Connections for Single-Supply Operation
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