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參數(shù)資料
| 型號： | ADG738BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | CMOS, Low-Voltage, 3-Wire Serially-Controlled, Matrix Switches |
| 中文描述： | 8-CHANNEL, AUDIO/VIDEO SWITCH, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 156K |
| 代理商： | ADG738BRU |
–10–
REV. 0
ADG738/ADG739
SCLK
DIN
DOUT
ADG739
SCLK
DIN
ADG739
SCLK
DIN
DOUT
DOUT
SCLK
DIN
SYNC
TO OTHER
SERIAL DEVICES
ADG739
V
DD
R
SYNC
SYNC
SYNC
R
R
Figure 20. Multiple ADG739 Devices in a Daisy-Chained Configuration
MC68HC11 Interface to ADG738/ADG739
Figure 18 shows an example of a serial interface between the
ADG738/ADG739 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the Matrix Switch, while the
MOSI output drives the serial data line, DIN.
SYNC
is driven
from one of the port lines, in this case PC7.
SCLK
DIN
SYNC
PC7
MOSI
SCK
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADG738/
ADG739
Figure 18. MC68HC11 Interface to ADG738/ADG739
The 68HC11 is configured for master mode; MSTR = 1, CPOL
= 0 and CPHA = 1. When data is transferred to the part, PC7 is
taken low, data is transmitted MSB first. Data appearing on the
MOSI output is valid on the falling edge of SCK.
If the user wishes to verify the data previously written to the input
shift register, the DOUT line could be connected to MISO of
the MC68HC11, and with
SYNC
low, the shift register would
clock data out on the rising edges of SCLK.
APPLICATIONS
Expand the Number of Selectable Serial Devices Using an
ADG739
The dual 4-channel ADG739 multiplexer can be used to multiplex
a single chip select line in order to provide chip selects for up to
four devices on the SPI bus. Figure 19 illustrates the ADG739 in
such a typical configuration. All devices receive the same serial
clock and serial data, but only one device will receive the
SYNC
signal at any one time. The ADG739 is a serially controlled
device also. One bit programmable pin of the microcontroller is
used to enable the ADG739 via
SYNC2
, while another bit
programmable pin is used as the chip select for the other serial
devices,
SYNC1
. Driving
SYNC2
low enables changes to be
made to the addressed serial devices. By bringing
SYNC1
low,
the selected serial device hanging from the SPI bus will be enabled
and data will be clocked into its shift register on the falling
edges of SCLK. The convenient design of the matrix switch
allows for different combinations of the four serial devices to
be addressed at any one time. If more devices need to be addressed
via one chip select line, the ADG738 is an 8-channel device and
would allow further expansion of the chip select scheme. There
may be some digital feedthrough from the digital input lines
because SCLK and DIN are permanently connected to each
device. Using a burst clock will minimize the effects of digital
feedthrough on the analog channels.
DA
1/2 OF ADG739
V
DD
SCLK
DIN
SYNC
S1A
S2A
S3A
S4A
SYNC1
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
DIN
SCLK
ADG739
SYNC
ADG738
OTHER SPI
DEVICE
SYNC2
FROM
CONTROLLER
OR DSP
OTHER SPI
DEVICE
Figure 19. Addressing Multiple Serial Devices Using an
ADG739
Daisy-Chaining Multiple ADG738s
A number of ADG738 matrix switches may be daisy-chained
simply by using the DOUT pin. DOUT is an open drain output
that should be pulled to the supply with an external resistor.
Figure 20 shows a typical implementation. The
SYNC
pin of all
three parts in the example are tied together. When
SYNC
is
brought low, the input shift registers of all parts are enabled,
data is written to the parts via DIN, and clocked through the
shift registers. When the transfer is complete,
SYNC
is brought
high and all switches are updated simultaneously. Further shift
registers may be added in series.
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