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參數(shù)資料
| 型號(hào)： | ADG733 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS, 2.5 ohm Low Voltage, Triple/Quad SPDT Switches |
| 中文描述： | 的CMOS，2.5歐姆的低電壓，三/四路SPDT開關(guān) |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 177K |
| 代理商： | ADG733 |
REV. 0
ADG733/ADG734
–6–
Table I. ADG733 Truth Table
A2
A1
A0
EN
ON Switch
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
None
D1-S1A, D2-S2A, D3-S3A
D1-S1B, D2-S2A, D3-S3A
D1-S1A, D2-S2B, D3-S3A
D1-S1B, D2-S2B, D3-S3A
D1-S1A, D2-S2A, D3-S3B
D1-S1B, D2-S2A, D3-S3B
D1-S1A, D2-S2B, D3-S3B
D1-S1B, D2-S2B, D3-S3B
X = Don’t Care.
Table II. ADG734 Truth Table
Logic
Switch A
Switch B
0
1
OFF
ON
ON
OFF
V
DD
V
SS
Most Positive Power Supply Potential.
Most Negative Power Supply in a Dual Supply
Application. In single supply applications, this
should be tied to ground close to the device.
Positive Supply Current.
Negative Supply Current.
Ground (0 V) Reference.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input.
Analog Voltage on Terminals D, S
Ohmic Resistance between D and S.
On Resistance Match between Any Two
Channels, i.e., R
ON
max – R
ON
min
Flatness is defined as the difference between the
maximum and minimum value of on-resistance
as measured over the specified analog signal range.
Source Leakage Current with the Switch
“OFF.”
Channel Leakage Current with the Switch
“ON.”
Maximum Input Voltage for Logic “0.”
Minimum Input Voltage for Logic “1.”
Input Current of the Digital Input.
“OFF” Switch Source Capacitance.
Measured with reference to ground.
“ON” Switch Capacitance. Measured
with reference to ground.
I
DD
I
SS
GND
S
D
IN
V
D
(V
S
)
R
ON
R
ON
R
FLAT(ON)
I
S
(OFF)
I
D
, I
S
(ON)
V
INL
V
INH
I
INL
(I
INH
)
C
S
(OFF)
C
D
, C
S
(ON)
C
IN
t
ON
Digital Input Capacitance.
Delay time measured between the 50% and
90% points of the digital inputs and the
switch “ON” condition.
Delay time measured between the 50% and
90% points of the digital input and the switch
“OFF” condition.
Delay time between the 50% and 90% points
of the
EN
digital input and the switch “ON”
condition.
Delay time between the 50% and 90% points
of the
EN
digital input and the switch “OFF”
condition.
“OFF” time measured between the 80%
points of both switches when switching from
one address state to another.
A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
A measure of unwanted signal coupling
through an “OFF” switch.
A measure of unwanted signal that is coupled
through from one channel to
another as a result of parasitic capacitance.
The frequency at which the output is
attenuated by 3 dBs.
The Frequency Response of the “ON” Switch.
Insertion Loss The loss due to the ON resistance of the switch.
t
OFF
t
ON
(
EN
)
t
OFF
(
EN
)
t
OPEN
Charge
Injection
Off Isolation
Crosstalk
Bandwidth
On Response
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