參數(shù)資料
型號(hào): ADG715BRU
廠商: ANALOG DEVICES INC
元件分類: 運(yùn)動(dòng)控制電子
英文描述: CMOS, Low Voltage Serially-Controlled, Octal SPST Switches
中文描述: OCTAL 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO24
封裝: MO-153AD, TSSOP-24
文件頁數(shù): 8/16頁
文件大?。?/td> 173K
代理商: ADG715BRU
ADG714/ADG715
–8–
REV. 0
ADG714 PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. These devices can accommodate serial input rates of up to 30 MHz.
Positive Analog Supply Voltage.
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial
clock input.
Ground Reference.
Source. May be an input or output.
2
3
V
DD
DIN
4
5, 7, 9, 11, 14,
16, 18, 20
6, 8, 10, 12, 13,
15, 17, 19
21
22
GND
Sx
Dx
Drain. May be an input or output.
V
SS
DOUT
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
Serial Data Output. This allows a number a parts to be daisy chained. Data is clocked out of
the input shift register on the rising edge of SCLK. DOUT is an open-drain output that should be
pulled to the supply with an external pull-up resistor.
Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC
goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled.
Data is transferred on the falling edges of the following clocks. Taking
SYNC
high updates the
switches.
23
24
RESET
SYNC
ADG715 PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 8-bit input
shift register. Clock rates of up to 400 kbit/s can be accommodated with this 2-wire serial interface.
Positive Analog Supply Voltage.
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 8-bit input
shift register during the write cycle and used to readback one byte of data during the read cycle. It
is a bidirectional open-drain data line which should be pulled to the supply with an external pull-
up resistor.
Ground Reference.
Source. May be an input or output.
2
3
V
DD
SDA
4
5, 7, 9, 11, 14,
16, 18, 20
6, 8, 10, 12, 13,
15, 17, 19
21
22
23
24
GND
Sx
Dx
Drain. May be an input or output.
V
SS
A1
RESET
A0
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
Address Input. Sets the second least significant bit of the 7-bit slave address.
Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
Address Input. Sets the least significant bit of the 7-bit slave address.
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