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參數(shù)資料
| 型號(hào)： | ADG715 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | REC3-SRW_DRW/H* Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 15V; Power: 3W; 2kV, 4kVDC & 6kVDC Isolation; Industry Standard 3W DIP24 Package; Feedback Regulated Output; Continuous Short Circuit Protection; Wide Input 2:1 & 4:1; Medical Approvals (4kV/6kV Versions); EN and UL Certificates; 3 Pinout Options, 3 Case Styles; Control Pin Option; Efficiency to 86% |
| 中文描述： | 的CMOS低電壓串行控制，八SPST開關(guān) |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 173K |
| 代理商： | ADG715 |
ADG714/ADG715
–13–
REV. 0
A repeated write function gives the user flexibility to update the
matrix switch a number of times after addressing the part only
once. During the write cycle, each data byte will update the con-
figuration of the switches. For example, after the matrix switch
has acknowledged its address byte, and received one data byte,
the switches will update after the data byte; if another data byte
is written to the matrix switch while it is still the addressed slave
device, this data byte will also cause a switch configuration update.
Repeat read of the matrix switch is also allowed.
Input Shift Register
The input shift register is eight bits wide. Figure 18 illustrates
the contents of the input shift register. Data is loaded into the
device as an 8-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure
2. The 8-bit word consists of eight data bits, each controlling
one switch. MSB (Bit 7) is loaded first.
Write Operation
When writing to the ADG715, the user must begin with an address
byte and R/
W
bit, after which the switch will acknowledge that
it is prepared to receive data by pulling SDA low. This address
byte is followed by the 8-bit word. The write operation for the
switch is shown in the Figure 19 below.
READ Operation
When reading data back from the ADG715, the user must begin
with an address byte and R/
W
bit, after which the switch will
acknowledge that it is prepared to transmit data by pulling SDA
low. The readback operation is a single byte that consists of the
eight data bits in the input register. The read operation for the
part is shown in Figure 20.
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
0
0
1
0
A0
R/W
STOP
COND
BY
MASTER
ACK
BY
ADG715
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
ACK
BY
ADG715
A1
1
Figure 19. ADG715 Write Sequence
SCL
SDA
S8
S7
S6
S5
S4
S3
S2
S1
0
0
1
0
A0
R/
W
STOP
COND
BY
MASTER
ACK
BY
ADG715
START
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
NO ACK
BY
MASTER
A1
1
Figure 20. ADG715 Readback Sequence
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is the
address byte that consists of the 7-bit slave address followed
by a R/
W
bit (this bit determines whether data will be read
from or written to the slave device).
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is termed the acknowledge bit). At this stage,
all other devices on the bus remain idle while the selected
device waits for data to be written to or read from its serial
register. If the R/
W
bit is high, the master will read from the
slave device. However, if the R/
W
bit is low, the master will
write to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
3. When all data bits have been read or written, a STOP con-
dition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition. In read mode, the master will issue a no acknowledge
for the ninth clock pulse (i.e., the SDA line remains high).
The master will then bring the SDA line low before the tenth
clock pulse and then high during the tenth clock pulse to estab-
lish a STOP condition.
See Figure 19 for a graphical explanation of the serial interface.
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| ADG715BRU | 功能描述:IC SWITCH OCTAL SPST 24TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
| ADG715BRU-REEL | 功能描述:IC SWITCH OCTAL SPST 24TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 功能:多路復(fù)用器 電路:1 x 4:1 導(dǎo)通狀態(tài)電阻:- 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±5V 電流 - 電源:7mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ADG715BRU-REEL7 | 功能描述:IC SWITCH OCTAL SPST 24TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 功能:多路復(fù)用器 電路:1 x 4:1 導(dǎo)通狀態(tài)電阻:- 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±5V 電流 - 電源:7mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ADG715BRUZ | 功能描述:IC SWITCH OCTAL SPST 24TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 特色產(chǎn)品:MicroPak? 標(biāo)準(zhǔn)包裝:1 系列:- 功能:開關(guān) 電路:2 x SPST - NC 導(dǎo)通狀態(tài)電阻:500 毫歐 電壓電源:單電源 電壓 - 電源，單路/雙路(±):1.4 V ~ 4.3 V 電流 - 電源:150nA 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-XFDFN 供應(yīng)商設(shè)備封裝:8-XSON，SOT833-1 （1.95x1） 包裝:Digi-Reel® 其它名稱:568-5557-6 |
| ADG715BRUZ-REEL | 功能描述:IC SWITCH OCTAL SPST 24TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 功能:多路復(fù)用器 電路:1 x 4:1 導(dǎo)通狀態(tài)電阻:- 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±5V 電流 - 電源:7mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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