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參數(shù)資料
| 型號(hào)： | ADG707BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | CMOS, 2.5ohm Low-Voltage, 8-/16-Channel Multiplexers |
| 中文描述： | 8-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | ADG707BRU |
–6–
REV. 0
ADG706/ADG707
A3
A2
A1
A0
EN
ON Switch
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X = Don’t Care.
Table II. ADG707 Truth Table
A2
A1
A0
EN
ON Switch Pair
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
8
X = Don’t Care.
TERMINOLOGY
V
DD
V
SS
Most Positive Power Supply Potential.
Most Negative Power Supply in a Dual Sup-
ply Application. In single supply applications,
this should be tied to ground at the device.
Positive Supply Current.
Negative Supply Current.
Ground (0 V) Reference.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input.
Analog Voltage on Terminals D, S.
Ohmic Resistance Between D and S.
On Resistance Match Between any Two Chan-
nels, i.e., R
ON
max – R
ON
min.
Flatness is defined as the difference between
the maximum and minimum value of on
resistance as measured over the specified analog
signal range.
Source Leakage Current with the Switch
“OFF.”
Drain Leakage Current with the Switch “OFF.”
Channel Leakage Current with the Switch
“ON.”
Maximum Input Voltage for Logic “0.”
Minimum Input Voltage for Logic “1.”
Input Current of the Digital Input.
“OFF” Switch Source Capacitance. Measured
with reference to ground.
I
DD
I
SS
GND
S
D
IN
V
D
(V
S
)
R
ON
R
ON
R
FLAT(ON)
I
S
(OFF)
I
D
(OFF)
I
D
, I
S
(ON)
V
INL
V
INH
I
INL
(I
INH
)
C
S
(OFF)
C
D
(OFF)
“OFF” Switch Drain Capacitance. Measured
with reference to ground.
“ON” Switch Capacitance. Measured with
reference to ground.
Digital Input Capacitance.
Delay Time Measured Between the 50% and
90% Points of the Digital Inputs and the Switch
“ON” Condition when Switching from One
Address State to Another.
Delay Time Between the 50% and 90% Points
of the EN Digital Input and the Switch “ON”
Condition.
Delay Time Between the 50% and 90% Points
of the EN Digital Input and the Switch “OFF”
Condition.
“OFF” Time Measured Between the 80%
Points of Both Switches when Switching from
One Address State to Another.
A Measure of the Glitch Impulse Transferred
from the Digital Input to the Analog Output
During Switching.
A Measure of Unwanted Signal Coupling
through an “OFF” Switch.
A Measure of Unwanted Signal which is
Coupled through from One Channel to
Another as a Result of Parasitic Capacitance.
The Frequency at which the Output Is
Attenuated by 3 dBs.
The Frequency Response of the “ON” Switch.
The Loss Due to the ON Resistance of the
Switch.
C
D
, C
S
(ON)
C
IN
t
TRANSITION
t
ON
(EN)
t
OFF
(EN)
t
OPEN
Charge
Injection
Off Isolation
Crosstalk
Bandwidth
On Response
Insertion
Loss
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