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參數(shù)資料
| 型號(hào)： | ADG433BRZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 多路復(fù)用及模擬開關(guān) |
| 英文描述： | LC2MOS Precision Quad SPST Switch; Package: SOIC; No of Pins: 16; Temperature Range: Industrial |
| 中文描述： | QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 131K |
| 代理商： | ADG433BRZ |
ADG431/ADG432/ADG433
REV. C
–6–
FREQUENCY
–
Hz
120
100
40
100
10M
1k
O
–
10k
100k
1M
80
60
V
DD
= +15V
V
SS
=
–
15V
V
L
= +5V
TPC 7. Off Isolation vs. Frequency
FREQUENCY
–
Hz
110
100
60100
10M
1k
C
–
10k
100k
1M
90
80
70
V
DD
= +15V
V
SS
=
–
15V
V
L
= +5V
TPC 8. Crosstalk vs. Frequency
TRENCH ISOLATION
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors from a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. A silicon-controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant
amplification of the current which, in turn, leads to latch up.
With trench isolation, this diode is removed, the result being a
latch-up proof switch.
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
T
R
E
N
C
H
T
R
E
N
C
H
T
R
E
N
C
H
P
+
P
+
P-CHANNEL
N
+
N
+
N-CHANNEL
P
–
N
–
V
G
V
D
V
S
V
G
V
D
V
S
Figure 1. Trench Isolation
APPLICATION
Figure 2 illustrates a precise, fast sample-and-hold circuit.
An AD845 is used as the input buffer while the output opera-
tional amplifier is an AD711. During the track mode, SW1 is
closed and the output V
OUT
follows the input signal V
IN
. In
the hold mode, SW1 is opened and the signal is held by the
hold capacitor C
H
.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a
polystyrene hold capacitor. The droop rate for the circuit
shown is typically 30
μ
V/
μ
s.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
C
and C
C
. This compensation network also reduces
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal error
has a maximum value of 5 mV over the
±
10 V input range. Both
the acquisition and settling times are 850 ns.
+15V
–
15V
2200pF
R
C
75
C
1000pF
C
H
2200pF
V
OUT
ADG431
ADG432
ADG433
SW1
SW2
S
S
D
D
+15V
+5V
–
15V
AD845
+15V
–
15V
V
IN
AD711
Figure 2. Fast, Accurate Sample-and-Hold
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|---|---|
| ADG433BRZ | 制造商:Analog Devices 功能描述:Multiplexer IC |
| ADG433BRZ-REEL | 功能描述:IC SWITCH QUAD SPST 16SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:LC²MOS 標(biāo)準(zhǔn)包裝:1,000 系列:- 功能:多路復(fù)用器 電路:1 x 4:1 導(dǎo)通狀態(tài)電阻:- 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±5V 電流 - 電源:7mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ADG436 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual SPDT Switch |
| ADG436_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual SPDT Switch |
| ADG436BN | 功能描述:IC SWITCH DUAL SPDT 16DIP RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:LC²MOS 標(biāo)準(zhǔn)包裝:48 系列:- 功能:開關(guān) 電路:4 x SPST - NO 導(dǎo)通狀態(tài)電阻:100 歐姆 電壓電源:單/雙電源 電壓 - 電源，單路/雙路(±):2 V ~ 12 V，±2 V ~ 6 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
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