參數(shù)資料
型號: ADG413BRZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 16SOIC
產(chǎn)品培訓(xùn)模塊: Switch Fundamentals
標(biāo)準(zhǔn)包裝: 2,500
系列: LC²MOS
功能: 開關(guān)
電路: 4 x SPST - NC/NO
導(dǎo)通狀態(tài)電阻: 80 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 12V,±15V
電流 - 電源: 100pA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 帶卷 (TR)
ADG411/ADG412/ADG413
Rev. D | Page 10 of 16
APPLICATIONS
Figure 13 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output VOUT follows the input signal VIN. In the hold
mode, SW1 is opened and the signal is held by the hold
capacitor CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor decreases with time. The ADG411/ADG412/ADG413
minimizes this droop due to its low leakage specifications. The
droop rate is further minimized by the use of a polystyrene
hold capacitor. The droop rate for the circuit shown is typically
30 μV/μs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches are at the same potential, they have a differential effect
on the op amp AD711, which minimizes charge injection
effects. Pedestal error is also reduced by the compensation
network RC and CC. This compensation network also reduces
the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the ±10 V
input range. Both the acquisition and settling times are 850 ns.
00024-
013
+15V
–15V
2200pF
RC
75
Ω
CC
1000pF
CH
2200pF
VOUT
ADG411
ADG412
ADG413
SW2
SW1
S
D
+15V
+5V
–15V
AD845
+15V
–15V
VIN
AD711
Figure 13. Fast, Accurate Sample-and-Hold
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