參數(shù)資料
型號: ADG412TQ
廠商: ANALOG DEVICES INC
元件分類: 運(yùn)動控制電子
英文描述: LC2MOS Precision Quad SPST Switches
中文描述: QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP16
封裝: CERDIP-16
文件頁數(shù): 6/8頁
文件大小: 156K
代理商: ADG412TQ
ADG411/ADG412/ADG413
REV. A
–6–
FREQUENCY – Hz
120
100
40
100
10M
1k
O
10k
100k
1M
80
60
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
Figure 7. Off Isolation vs. Frequency
FREQUENCY – Hz
110
100
60100
10M
1k
C
10k
100k
1M
90
80
70
V
DD
= +15V
V
SS
= –15V
V
L
= +5V
Figure 8. Crosstalk vs. Frequency
APPLICAT ION
Figure 9 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V
OUT
follows the input signal V
IN
. In the hold
mode, SW1 is opened and the signal is held by the hold capaci-
tor C
H
.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. T he ADG411/ADG412/
ADG413 minimizes this droop due to its low leakage specifica-
tions. T he droop rate is further minimized by the use of a poly-
styrene hold capacitor. T he droop rate for the circuit shown is
typically 30
μ
V/
μ
s.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711, which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
C
and C
C
. T his compensation network also re-
duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes-
tal error has a maximum value of 5 mV over the
±
10 V input
range. Both the acquisition and settling times are 850 ns.
+15V
–15V
2200pF
R
C
75
V
C
1000pF
C
H
2200pF
V
OUT
ADG411
ADG412
ADG413
SW2
SW1
S
S
D
D
+15V
+5V
–15V
AD845
+15V
–15V
V
IN
AD711
Figure 9. Fast, Accurate Sample-and-Hold
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