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參數(shù)資料
| 型號： | ADG407 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC2MOS 8-/16-Channel High Performance Analog Multiplexers |
| 中文描述： | LC2MOS 8-/16-Channel高性能模擬多路復(fù)用器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 378K |
| 代理商： | ADG407 |
–6–
ADG406/ADG407/ADG426
REV. 0
TIMING DIAGRAMS (ADG426)
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while
WR
is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of
WR
.
Figure 2.
Figure 2 shows the Reset Pulse Width, t
RS
, and the Reset Turn
Off Time, t
OFF
(
RS
).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. t
R
= t
F
= 20 ns.
TERMINOLOGY
V
DD
V
SS
Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
Ground (0 V) reference.
Ohmic resistance between D and S.
Difference between the R
ON
of any two
channels.
Source leakage current when the switch is off.
Drain leakage current when the switch is off.
Channel leakage current when the switch
is on.
Analog voltage on terminals D, S.
Channel input capacitance for “OFF”
condition.
Channel output capacitance for “OFF”
condition.
“ON” switch capacitance.
Digital input capacitance.
Delay time between the 50% and 90%
points of the digital input and switch “ON”
condition.
Delay time between the 50% and 90%
points of the digital input and switch “OFF”
condition.
Delay time between the 50% and 90%
points of the digital inputs and the switch
“ON” condition when switching from one
address state to another.
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
Maximum input voltage for logic “0.”
Minimum input voltage for logic “1.”
Input current of the digital input.
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
A measure of unwanted signal coupling
through an “OFF” channel.
A measure of the glitch impulse
transferred from the digital input to the analog
output during switching.
Positive supply current.
Negative supply current.
GND
R
ON
R
ON
Match
I
S
(OFF)
I
D
(OFF)
I
D
, I
S
(ON)
V
D
(V
S
)
C
S
(OFF)
C
D
(OFF)
C
D
, C
S
(ON)
C
IN
t
ON
(EN)
t
OFF
(EN)
t
TRANSITION
t
OPEN
V
INL
V
INH
I
INL
(I
INH
)
Crosstalk
Off Isolation
Charge
Injection
I
DD
I
SS
50%
t
W
50%
t
S
2V
0.8V
t
H
3V
WR
0V
3V
A0, A1, A2, (A3)
EN
0V
50%
t
RS
50%
0.8V
0
3V
0V
V
0
0V
RS
t
OFF
(
RS
)
SWITCH
OUTPUT
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| ADG407BCHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS 8-/16-Channel High Performance Analog Multiplexers |
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| ADG407BNZ | 功能描述:IC MULTIPLEXER DUAL 8X1 28DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:LC²MOS 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 功能:開關(guān) 電路:單刀單擲 導(dǎo)通狀態(tài)電阻:48 歐姆 電壓電源:單電源 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電流 - 電源:5µA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:托盤 |
| ADG407BP | 功能描述:IC MULTIPLEXER DUAL 8X1 28PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:LC²MOS 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
| ADG407BP-REEL | 功能描述:IC MULTIPLEXER DUAL 8X1 28PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:LC²MOS 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
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