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參數資料
| 型號： | ADG3304BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XLATR BIDIR V-LVL 4CH 14TSSOP |
| 標準包裝： | 1,000 |
| 邏輯功能： | 變換器，雙向 |
| 位數： | 4 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 數據速率： | 50Mbps |
| 通道數： | 4 |
| 輸出/通道數目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 6ns |
| 電源電壓： | 1.15 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | ADG3304BRUZ-REEL7-ND ADG3304BRUZ-REEL7TR |
Data Sheet
ADG3304
Rev. D | Page 15 of 20
TERMINOLOGY
VIHA
Logic input high voltage at Pin A1 to Pin A4.
VILA
Logic input low voltage at Pin A1 to Pin A4.
VOHA
Logic output high voltage at Pin A1 to Pin A4.
VOLA
Logic output low voltage at Pin A1 to Pin A4.
CA
Capacitance measured at Pin A1 to Pin A4 (EN = 0).
ILA, Hi-Z
Leakage current at Pin A1 to Pin A4 when EN = 0 (high
impedance state at Pin A1 to Pin A4).
VIHY
Logic input high voltage at Pin Y1 to Pin Y4.
VILY
Logic input low voltage at Pin Y1 to Pin Y4.
VOHY
Logic output high voltage at Pin Y1 to Pin Y4.
VOLY
Logic output low voltage at Pin Y1 to Pin Y4.
CY
Capacitance measured at Pin Y1 to Pin Y4 (EN = 0).
ILY, Hi-Z
Leakage current at Pin Y1 to Pin Y4 when EN = 0 (high
impedance state at Pin Y1 to Pin Y4).
VIHEN
Logic input high voltage at the EN pin.
VILEN
Logic input low voltage at the EN pin.
CEN
Capacitance measured at EN pin.
ILEN
Enable (EN) pin leakage current.
tEN
Three-state enable time for Pin A1 to Pin A4 and Pin Y1 to
Pin Y4.
tP, A→Y
Propagation delay when translating logic levels in the A→Y
direction.
tR, A→Y
Rise time when translating logic levels in the A→Y direction.
TF, A→Y
Fall time when translating logic levels in the A→Y direction.
DMAX, A→Y
Guaranteed data rate when translating logic levels in the A→Y
direction under the driving and loading conditions specified in
TSKEW, A→Y
Difference between propagation delays on any two channels
when translating logic levels in the A→Y direction.
tPPSKEW, A→Y
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the A→Y direction.
tP, Y→A
Propagation delay when translating logic levels in the Y→A
direction.
tR, Y→A
Rise time when translating logic levels in the Y→A direction.
tF, Y→A
Fall time when translating logic levels in the Y→A direction.
DMAX, Y→A
Guaranteed data rate when translating logic levels in the Y→A
direction under the driving and loading conditions specified in
tSKEW, Y→A
Difference between propagation delays on any two channels
when translating logic levels in the Y→A direction.
tPPSKEW, Y→A
Difference in propagation delay between any one channel and
the same channel on a different part (under the same driving/
loading conditions) when translating in the Y→A direction.
VCCA
VCCA supply voltage.
VCCY
VCCY supply voltage.
ICCA
VCCA supply current.
ICCY
VCCY supply current.
IHi-Z, A
VCCA supply current during three-state mode (EN = 0).
IHi-Z, Y
VCCY supply current during three-state mode (EN = 0).
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