
ADG3257
Rev. E | Page 3 of 12
SPECIFICATIONS
VCC = 5.0 V ± 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Symbol
B Version
Unit
Min
Max
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
2.4
V
Input Low Voltage
VINL
0.3
+0.8
V
Input Leakage Current
II
0 ≤ VIN ≤ 5.5 V
±0.01
±1
μA
Off State Leakage Current
IOZ
0 ≤ A, B ≤ VCC
±0.01
±1
μA
On State Leakage Current
IOZ
0 ≤ A, B ≤ VCC
±0.01
±1
μA
VP
VIN = VCC = 5 V, IO = 5 μA
3.9
4.2
4.4
V
A Port Off Capacitance
CA OFF
f = 1 MHz
7
pF
B Port Off Capacitance
CB OFF
f = 1 MHz
5
pF
A, B Port On Capacitance
CA, CB ON
f = 1 MHz
11
pF
Control Input Capacitance
CIN
f = 1 MHz
4
pF
SWITCHING CHARACTERIST
ICS4Propagation Delay A to B or B to A, tPD
VA = 0 V, CL = 50 pF
0.10
ns
VA = 0 V, CL = 50 pF
0.0075
0.035
ns
Bus Enable Time BE to A or B
tPZH, tPZL
CL = 50 pF, RL = 500 Ω
1
5
7.5
ns
Bus Disable Time BE to A or B
tPHZ, tPLZ
CL = 50 pF, RL = 500 Ω
1
3.5
7
ns
Bus Select Time S to A or B
Enable
tSEL_EN
CL = 50 pF, RL = 500 Ω
8
12
ns
Disable
tSEL_DIS
CL = 50 pF, RL = 500 Ω
5
8
ns
Maximum Data Rate
VA = 2 V p-p
933
Mbps
DIGITAL SWITCH
On Resistance
RON
VA = 0 V
IO = 48 mA, 15 mA, 8 mA, TA = 25°C
2
4
Ω
IO = 48 mA, 15 mA, 8 mA
5
Ω
VA = 2.4 V
IO = 48 mA, 15 mA, 8 mA, TA = 25°C
3
6
Ω
IO = 48 mA, 15 mA, 8 mA
7
Ω
On-Resistance Matching
ΔRON
VA = 0 V, IO = 48 mA, 15 mA, 8 mA
0.15
Ω
POWER REQUIREMENTS
VCC
3.0
5.5
V
Quiescent Power Supply Current
ICC
Digital inputs = 0 V or VCC
0.001
1
μA
ΔICC
VCC = 5.5 V, one input at 3.0 V; others at VCC or GND
200
μA
1 Temperature range is: Version B: –40°C to +85°C.
3 All typical values are at TA = 25°C, unless otherwise noted.
4 Guaranteed by design, not subject to production test.
5 The digital switch contributes no propagation delay other than the RC delay of the typical RON
source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6 Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance.
7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute
no significant ac or dc currents as they transition.