參數(shù)資料
型號： ADG3257
廠商： Analog Devices, Inc.
英文描述： High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch
中文描述： 高速，3.3伏/ 5伏四路2:1復(fù)用/解復(fù)用（4位，2 1）總線開關(guān)
文件頁數(shù)： 2/8頁
文件大?。?/td> 173K
代理商： ADG3257
REV. C
–2–
ADG3257–SPECIFICATIONS
1
(V
CC
= 5.0 V 10%, GND = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
B Version
Typ
3
Parameter
Symbol
Conditions
2
Min
Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Leakage Current
OFF State Leakage Current
ON State Leakage Current
Max Pass Voltage
4
V
INH
V
INL
I
I
I
OZ
I
OZ
V
P
2.4
–0.3
V
V
μ
A
μ
A
μ
A
V
+0.8
±
1
±
1
±
1
4.4
0 V
IN
5.5 V
0 A, B V
CC
0 A, B V
CC
V
IN
= V
CC
= 5 V, I
O
= –5
μ
A
±
0.01
±
0.01
±
0.01
4.2
3.9
CAPACITANCE
4
A Port OFF Capacitance
B Port OFF Capacitance
A, B Port ON Capacitance
Control Input Capacitance
C
A
OFF
C
B
OFF
C
A
, C
B
ON
C
IN
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
7
5
11
4
pF
pF
pF
pF
SWITCHING CHARACTERISTICS
4
Propagation Delay A to B or B to A
t
PD
Propagation Delay Matching
6
Bus Enable Time
BE
to A or B
Bus Disable Time
BE
to A or B
Bus Select Time S to A or B
Enable
Disable
Max Data Rate
t
PHL
,
t
PLH5
V
A
= 0 V, C
L
= 50 pF
V
A
= 0 V, C
L
= 50 pF
C
L
= 50 pF, R
L
= 500
C
L
= 50 pF, R
L
= 500
0.10
ns
0.0075 0.035 ns
5
7.5
3.5
7
t
PZH
, t
PZL
t
PHZ
, t
PLZ
1
1
ns
ns
t
SEL_EN
t
SEL_DIS
C
L
= 50 pF, R
L
= 500
C
L
= 50 pF, R
L
= 500
V
A
= 2 V p-p
8
5
933
12
8
ns
ns
Mbps
DIGITAL SWITCH
ON Resistance
R
ON
V
A
= 0 V
I
O
= 48 mA, 15 mA, 8 mA, T
A
= 25
°
C
I
O
= 48 mA, 15 mA, 8 mA
V
A
= 2.4 V
I
O
= 48 mA, 15 mA, 8 mA, T
A
= 25
°
C
I
O
= 48 mA, 15 mA, 8 mA
V
A
= 0 V
48 mA, 15 mA, 8 mA, T
A
= 25
°
C
V
A
= 0 V, 48 mA, 15 mA, 8 mA
2
3
4
3
5
6
ON Resistance Matching
R
ON
0.15
0.35
0.7
POWER REQUIREMENTS
V
CC
Quiescent Power Supply Current
Increase in I
CC
per Input
7
3.0
5.5
1
V
μ
A
I
CC
I
CC
Digital Inputs = 0 V or V
CC
V
CC
= 5.5 V, One Input at 3.0 V;
Others at V
CC
or GND
0.001
200
μ
A
NOTES
1
Temperature range is as follows: B Version: –40
°
C to +85
°
C.
2
See Test Circuits and Waveforms.
3
All typical values are at T
A
= 25
°
C, unless otherwise noted.
4
Guaranteed by design, not subject to production test.
5
The digital switch contributes no propagation delay other than the RC delay of the typical R
ON
of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6
Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.
7
This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
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