參數(shù)資料
型號： ADG3249BRJ-R2
廠商： ANALOG DEVICES INC
元件分類： 運動控制電子
英文描述： 2.5 V/3.3 V, 2:1 Multiplexer/ Demultiplexer Bus Switch
中文描述： 2-CHANNEL, SGL ENDED MULTIPLEXER, PDSO8
封裝： MO-178BA, SOT-23, 8 PIN
文件頁數(shù)： 2/12頁
文件大?。?/td> 220K
代理商： ADG3249BRJ-R2
REV. 0
–2–
ADG3249–SPECIFICATIONS
1
B Version
Min
Typ
2
Parameter
Symbol
Conditions
Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
V
INH
V
INH
V
INL
V
INL
I
I
I
OZ
V
CC
= 2.7 V to 3.6 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 2.3 V to 2.7 V
2.0
1.7
V
V
V
V
μ
A
μ
A
μ
A
V
V
V
Input Low Voltage
0.8
0.7
±
1
±
1
±
1
2.9
2.1
2.1
Input Leakage Current
OFF State Leakage Current
ON State Leakage Current
Maximum Pass Voltage
±
0.01
±
0.01
±
0.01
2.5
1.8
1.8
0
≤
A, B
≤
V
CC
0
≤
A, B
≤
V
CC
V
A
/V
B
= V
CC
=
SEL
= 3.3 V, I
O
=
–
5
μ
A
V
A
/V
B
= V
CC
=
SEL
= 2.5 V, I
O
=
–
5
μ
A
V
A
/V
B
= V
CC
= 3.3 V,
SEL
= 0 V, I
O
=
–
5
μ
A
V
P
2.0
1.5
1.5
CAPACITANCE
3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
C
A
OFF
C
B
OFF
C
A
, C
B
ON
C
IN,
C
SEL
C
EN
f = 1 MHz;
EN
= V
CC
f = 1 MHz;
EN
= V
CC
f = 1 MHz
f = 1 MHz
f = 1 MHz
3.5
4.5
8.5
4
6.5
pF
pF
pF
pF
pF
SWITCHING CHARACTERISTICS
3
Propagation Delay A to B or B to A, t
PD4
Propagation Delay Matching
5
Bus Enable Time
EN
to A or B
6
Bus Disable Time
EN
to A or B
6
Bus Enable Time
EN
to A or B
6
Bus Disable Time
EN
to A or B
6
Bus Enable Time
EN
to A or B
6
Bus Disable Time
EN
to A or B
6
Break-before-Make Time
Transition Time
t
PHL
, t
PLH
C
L
= 50 pF, V
CC
=
SEL
= 3 V
0.225
5
4.8
8.2
4.5
7.7
4.6
5.8
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
Gbps
ps p-p
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
BBM
t
TRANS
V
CC
= 3.0 V to 3.6 V;
SEL
= V
CC
V
CC
= 3.0 V to 3.6 V;
SEL
= V
CC
V
CC
= 3.0 V to 3.6 V;
SEL
= 0 V
V
CC
= 3.0 V to 3.6 V;
SEL
= 0 V
V
CC
= 2.3 V to 2.7 V;
SEL
= V
CC
V
CC
= 2.3 V to 2.7 V;
SEL
= V
CC
R
L
= 510
, C
L
= 50 pF
R
L
= 510
, C
L
= 50 pF;
SEL
= V
CC
R
L
= 510
, C
L
= 50 pF;
SEL
= 0 V
V
CC
=
SEL
= 3.3 V; V
A
/V
B
= 2 V
V
CC
=
SEL
= 3.3 V; V
A
/V
B
= 2 V
1
1
1
1
1
1
5
3.5
5.5
3.2
4.5
3.5
4
10
16
15
1.244
45
29
22
Maximum Data Rate
Channel Jitter
DIGITAL SWITCH
On Resistance
R
ON
V
CC
= 3 V,
SEL
= V
CC
, V
A
= 0 V, I
BA
= 8 mA
V
CC
= 3 V,
SEL
= V
CC
, V
A
= 1.7 V, I
BA
= 8 mA
V
CC
= 2.3 V,
SEL
= V
CC
, V
A
= 0 V, I
BA
= 8 mA
V
CC
= 2.3 V,
SEL
= V
CC
, V
A
= 1 V, I
BA
= 8 mA
V
CC
= 3 V,
SEL
= 0 V V
A
= 0 V, I
BA
= 8 mA
V
CC
= 3 V,
SEL
= 0 V, V
A
= 1 V, I
BA
= 8 mA
V
CC
= 3 V,
SEL
= V
CC
, V
A
= 0 V, I
A
= 8 mA
V
CC
= 3 V,
SEL
= 0 V, V
A
= 0 V, I
A
= 8 mA
4.5
12
5
9
5
12
0.1
0.1
8
28
9
18
8
On Resistance Matching
R
ON
0.5
0.5
POWER REQUIREMENTS
V
CC
Quiescent Power Supply Current
2.3
3.6
1
0.2
8
V
μ
A
mA
μ
A
I
CC
Digital Inputs = 0 V or V
CC
;
SEL
= V
CC
Digital Inputs = 0 V or V
CC
;
SEL
= 0 V
V
CC
= 3.6 V,
EN
= 3.0 V;
SEL
= V
CC
; IN = V
CC
0.01
0.1
0.15
Increase in I
CC
per Input
7
I
CC
NOTES
1
Temperature range is as follows: B Version:
–
40
°
C to +85
°
C.
2
Typical values are at 25
°
C, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical R
of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6
See Timing Measurement Information section.
7
This current applies to the control pin
EN
only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
(V
= 2.3 V to 3.6 V, GND = 0 V, all specifications T
MIN
to T
MAX
,
unless otherwise noted.)
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