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參數(shù)資料
型號: ADG3232BRJ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 7/8頁
文件大?。?/td> 0K
描述: IC SW LLT 1.65/3.6 LV SOT23-8
標準包裝: 1
邏輯功能: 變換器,雙向
位數(shù): 2
輸入類型: 邏輯
輸出類型: 邏輯
通道數(shù): 1
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 4ns,3.5ns
電源電壓: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標準包裝
其它名稱: ADG3232BRJ-REEL7DKR
ADG3232
–6–
ADG3232
–7–
TEST CIRCUITS
INPUT
0V
VOH
VOL
VCC1
VT
VL
tPLH
tPHL
OUTPUT
Figure 1. Propagation Delay
EN
tEN
Y2
tDIS
VT
0V
VOH
VCC1
VT
0V
VCC1
0V
VCC1
VOL
A1
A2
Figure 2. Enable and DisableTimes
DESCRIPTION
The ADG3232 is a mux level translating device designed on a
submicron process that operates from supplies as low as 1.65 V.
The device is guaranteed for operation over the supply range
1.65 V to 3.6 V. It operates from two supply voltages, allowing
bidirectional level translation, i.e., it translates lower voltages to
higher voltages and vice versa.The signal path is unidirectional,
meaning data may only flow from A toY.
A1 and EN Input
The A1 and enable (EN) inputs have VIL/VIH logic levels so that
the part can accept logic levels of VOL/VOH independent of the
value of the supply being used. Both these inputs (A1 and EN)
are capable of accepting inputs outside the VCC1 supply range.
There are no internal diodes to the supply rails on these pins, so
they can handle inputs above the supply but inside the absolute
maximum ratings.
Operation
Figure 3 shows the ADG3232 in a typical application; the signal
paths are from A1 or A2 toY. The device will level translate the signal
applied to A1/A2 from aVCC1 logic level (this level translation can
be either to a higher or a lower supply) and route the signal to the
Y output, which will have standard VOL/VOH levels forVCC2 supplies.
The supplies in Figure 3 may be any combination of supplies, e.g.,
VCC1 andVCC2 may be anywhere in the 1.65V to 3.6V range.
EN
Figure 3. Typical Operation of the ADG3232 LevelTranslating Switch
REV. A
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