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參數資料
| 型號： | ADG1423BRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SW SPST 2.1OHM RON 10MSOP |
| 標準包裝： | 1,000 |
| 系列： | iCMOS® |
| 功能： | 開關 |
| 電路： | 2 x SPST - NC/NO |
| 導通狀態(tài)電阻： | 4.6 歐姆 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 16.5 V，±2.25 V ~ 8.25 V |
| 電流 - 電源： | 120µA |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
ADG1421/ADG1422/ADG1423
Rev. 0 | Page 14 of 16
TERMINOLOGY
IDD
The positive supply current.
ISS
The negative supply current.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between Terminal D and Terminal S.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
CIN
The digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition. See Figure 26.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition. See Figure 26.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
TBBM
Off time measured between the 80% point of both switches
when switching from one address state to another. See Figure 27.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching. See Figure 28.
Off Isolation
A measure of unwanted signal coupling through an off switch.
See Figure 29.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance. See
Bandwidth
The frequency at which the output is attenuated by 3 dB. See
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch. See Figure 31.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental. See Figure 32.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR measures the ability of a part to avoid coupling noise
and spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on
the output to the amplitude of the modulation is the ACPSRR.
See Figure 22.
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