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參數(shù)資料
| 型號： | ADF4360-6BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 1.25GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4360-6EBZ1-ND - BOARD EVALUATION FOR ADF4360-6 |
Data Sheet
ADF4360-6
Rev. B | Page 11 of 24
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360 family are con-
nected to the collectors of an NPN differential pair driven by
buffered outputs of the VCO, as shown in Figure 15. To allow
the user to optimize the power dissipation versus the output
power requirements, the tail current of the differential pair is
programmable via Bits PL1 and PL2 in the control latch. Four
current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of 13.5 dBm, 10.5 dBm,
7.5 dBm, and 4.5 dBm, respectively, using a 50 resistor to
VDD and ac coupling into a 50 load. Alternatively, both out-
puts can be combined in a 1 + 1:1 transformer or a 180° mi-
crostrip coupler (see the Output Matching section).
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
mute-till-lock detect (MTLD) bit in the control latch.
VCO
RFOUTA
RFOUTB
BUFFER/
DIVIDE BY 2
04440-015
Figure 15. Output Stage ADF4360-6
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