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參數(shù)資料
| 型號： | ADF4360-2BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 2.17GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4360-2EBZ1-ND - BOARD EVALUATION FOR ADF4360-2 |
ADF4360-2
Data Sheet
Rev. C | Page 18 of 24
CONTROL LATCH
With (C2, C1) = (0, 0), the control latch is programmed. Table 7
shows the input data format for programming the control latch.
Prescaler Value
In the ADF4360 family, P2 and P1 in the control latch set the
prescaler values.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable power-
down modes.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 is loaded with a 0. In the programmed
synchronous power-down, the device power-down is gated by
the charge pump to prevent unwanted frequency jumps. Once
the power-down is enabled by writing a 1 into Bit PD1 (on the
condition that a 1 is also loaded to PD2), the device goes into
power-down on the second rising edge of the R counter output,
after LE goes high. When the CE pin is low, the device is
immediately disabled regardless of the state of PD1 or PD2.
When a power-down is activated (either synchronous or
asynchronous mode), the following events occur:
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF outputs are debiased to a high impedance state.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
Charge Pump Currents
CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1.
CPI6, CPI5, and CPI4 determine Current Setting 2. See the
truth table in Table 7.
Output Power Level
Bit PL1 and Bit PL2 set the output power level of the VCO. See
the truth table in Table 7.
Mute-Till-Lock Detect (LD)
DB11 of the control latch in the ADF4360 family is the mute-
till-lock detect bit. This function, when enabled, ensures that
the RF outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360 family is the charge
pump gain bit. When it is programmed to 1, Current Setting 2
is used. When it is programmed to 0, Current Setting 1 is used.
Charge Pump (CP) Three-State
This bit puts the charge pump into three-state mode when
programmed to a 1. It should be set to 0 for normal operation.
Phase Detector Polarity
The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active noninverting filter. It can also be set to 0, which is
required if an active inverting loop filter is used.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1.
See the truth table in Table 7.
Counter Reset
DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The
recommended setting is 15 mA for frequencies above 2 GHz
and 20 mA for frequencies below 2 GHz. No other settings are
valid. See the truth table in Table 7.
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