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參數(shù)資料
| 型號： | ADF4156BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FRAC-N FREQ SYNTH 16TSSOP |
| 產(chǎn)品變化通告： | Improve Phase Noise Performance |
| 設計資源： | Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174) |
| 標準包裝： | 1,000 |
| 類型： | 分數(shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 6.2GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADF4156
Rev. E | Page 21 of 24
INTERFACING
The ADF4156 has a simple SPI-compatible serial interface for
writing to the device. CLOCK, DATA, and LE control the data
transfer. When latch enable (LE) is high, the 29 bits that have
been clocked into the input register on each rising edge of serial
clock are transferred to the appropriate latch. The maximum
allowable serial clock rate is 20 MHz. See Figure 2 for the timing
diagram and Table 6 for the latch truth table.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the lead frame chip scale package (CP-20-6) are
rectangular. The printed circuit board pad for these lands should be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. The package land should be centered
on the pad to ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that shorting
is avoided.
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad on a 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz of
copper to plug the via. In addition, the printed circuit board
thermal pad should be connected to AGND.
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相關代理商/技術參數(shù) |
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| ADF4156SP1BRUZ | 制造商:Analog Devices 功能描述: |
| ADF4157 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
| ADF4157BCPZ | 功能描述:IC PLL FREQ SYNTH 6GHZ 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4157BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Resolution 6 GHz Fractional-N Frequency Synthesizer |
| ADF4157BCPZ-RL | 功能描述:IC PLL FREQ SYNTH 6GHZ 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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