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參數(shù)資料
| 型號(hào)： | ADF4112BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTH 3GHZ 20-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
| 配用： | EVAL-ADF4112EBZ1-ND - BOARD EVAL FOR ADF4112 EVAL-ADF411XEBZ1-ND - BOARD EVAL FOR ADF411X NO CHIP |
ADF4154
Data Sheet
Rev. C | Page 6 of 24
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
ADF4154
TOP VIEW
(Not to Scale)
AGND
4
RFINB 5
RFINA 6
AVDD 7
REFIN 8
LE
DATA
CLK
SDVDD
DGND
13
12
11
10
RSET 1
CP 2
CPGND
3
VP
DVDD
MUXOUT
16
15
14
9
04
83
3
-00
2
Figure 3. TSSOP Pin Configuration
048
33-
003
14
13
12
1
3
4
LE
15 MUXOUT
DATA
CLK
11 SDVDD
CPGND
AGND
2
AGND
RFINB
5
RFINA
7
A
V
D
6
A
V
D
8
R
E
F
IN
9
D
G
N
D
1
0
D
G
N
D
1
9
R
S
E
T
2
0
C
P
1
8
V
P
1
7
D
V
D
1
6
D
V
D
ADF4154
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
LFCSP
Mnemonic
Description
1
19
RSET
Set Resistor. Connecting a resistor between this pin and ground sets the maximum charge pump
output current. The relationship between ICP and RSET is
SET
CPmax
R
I
5
.
25
where RSET = 5.1 kΩ and ICPmax = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn
drives the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF (see Figure 15).
6
5
RFINA
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7
6, 7
AVDD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed
as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD.
8
REFIN
Reference Input. This CMOS input has a nominal threshold of VDD/2 and an equivalent input resistance of
100 kΩ (see Figure 14). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
SDVDD
Σ- Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to
this pin. SDVDD has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a
high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the
four latches, which is selected by the user via the control bits.
14
15
MUXOUT
Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
15
16, 17
DVDD
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same
voltage as AVDD.
16
18
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
N/A
EP
EPAD
Exposed Pad. The exposed pad must be connected to AGND.
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| ADF4112BCPZ-RL | 功能描述:IC PLL FREQ SYNTH 3GHZ 20-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4112BCPZ-RL7 | 功能描述:IC PLL FREQ SYNTH 3GHZ 20-LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4112BRU | 功能描述:IC SYNTH PLL RF 3.0GHZ 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4112BRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 16-Pin TSSOP T/R |
| ADF4112BRU-REEL7 | 功能描述:IC PLL FREQ SYNTHESIZER 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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