參數(shù)資料
型號: ADF4106BCP
廠商: ANALOG DEVICES INC
元件分類: XO, clock
英文描述: PLL Frequency Synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 6000 MHz, QCC20
封裝: 4 X 4 MM, MO-220VGGD-1, LFCSP-20
文件頁數(shù): 17/20頁
文件大?。?/td> 228K
代理商: ADF4106BCP
REV. 0
ADF4106
–17–
ADF4106
V940ME03
FREF
IN
RF
OUT
V
DD
V
P
V
CC
CE
CLK
DATA
LE
S
1000pF
1000pF
REFIN
NOTE
DECOUPLING CAPACITORS (0.1 F/10pF) ON AV
, DV
,
V
OF THE ADF4106 AND ON V
OF THE V940ME03 HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID
CLARITY.
100pF
AV
DD
DV
DD
VP
CP
MUXOUT
LOCK
DETECT
RF
IN
A
RF
IN
B
C
A
D
100pF
1.5nF
20pF
100pF
100pF
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
R
SET
5.1k
51
6.2k
4.3k
100pF
18
18
18
Figure 7. Local Oscillator for LMDS Base Station
INTERFACING
The ADF4106 has a simple SPI-compatible serial interface for
writing to the device. SCLK, SDATA and LE control the data
transfer. When LE (Latch Enable) goes high, the 24 bits which
have been clocked into the input register on each rising edge of
SCLK will get transferred to the appropriate latch. See Figure 1
for the Timing Diagram and Table I for the Latch Truth Table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz
or one update every 1.2
μ
s. This is certainly more than adequate
for systems which will have typical lock times in hundreds of
microseconds.
ADuC812 Interface
Figure 8 shows the interface between the ADF4106 and the
ADuC812 microconverter. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4106 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the microconverter to the device. When the third byte has
been written the LE input should be brought high to complete
the transfer.
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