參數(shù)資料
型號(hào)： ADE7758ARWZ
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC with Per Phase Information
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO24
封裝： LEAD FREE, MS-013-AD, SOIC-24
文件頁(yè)數(shù)： 7/68頁(yè)
文件大?。?/td> 1584K
代理商： ADE7758ARWZ
ADE7758
TIMING CHARACTERISTICS
1, 2
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, T
MIN
to T
MAX
= 40°C to +85°C.
Table 2.
Parameter
Specification Unit
Test Conditions/Comments
Write Timing
t
1
50
ns (min)
CS falling edge to first SCLK falling edge.
t
2
50
ns (min)
SCLK logic high pulse width.
t
3
50
ns (min)
SCLK logic low pulse width.
t
4
10
ns (min)
Valid data setup time before falling edge of SCLK.
t
5
5
ns (min)
Data hold time after SCLK falling edge.
t
6
900
ns (min)
Minimum time between the end of data byte transfers.
t
7
50
ns (min)
Minimum time between byte transfers during a serial write.
t
8
100
ns (min)
CS hold time after SCLK falling edge.
Read Timing
t
9
1.1
μs (min)
Minimum time between read command (i.e., a write to communication register) and data read.
t
10
50
ns (min)
Minimum time between data byte transfers during a multibyte read.
t
113
30
ns (min)
Data access time after SCLK rising edge following a write to the communications register.
t
124
100
ns (max)
Bus relinquish time after falling edge of SCLK.
10
ns (min)
t
134
100
ns (max)
Bus relinquish time after rising edge of CS.
10
ns (min)
Rev. A | Page 7 of 68
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
2
See the timing diagrams in
and
and the
Figure 3
Figure 4
ADE7758 Serial Interface
3
Measured with the load circuit in
and defined as the time required for the output to cross 0.8 V or 2.4 V.
Figure 2
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
section.
0
200
μ
A
I
OL
1.6mA
I
OH
2.1V
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Timing Specifications
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