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參數(shù)資料
| 型號： | ADE7752AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | LJT 41C 41#20 SKT PLUG |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 474K |
| 代理商： | ADE7752AR |
REV. PrB 08/01
PRELIMINARY TECHNICAL DATA
3–
ADE7752
TIMING CHARACTERISTICS
1, 2
Parameter
t
13
t
2
t
3
t
43, 4
t
5
t
6
Units
Test Conditions/Comments
275
See Table III
1/2 t
2
90
See Table IV
CLKIN/4
ms
sec
sec
ms
sec
sec
F1 and F2 Pulsewidth (Logic High)
Output Pulse Period. See Transfer Function Section
Time Between F1 Falling Edge and F2 Falling Edge
CF Pulsewidth (Logic High)
CF Pulse Period. See Transfer Function Section
Minimum Time Between F1 and F2 Pulse
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 1.
3
The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.
4
The CF pulse is always 1 μs in the high frequency mode. See Frequency Outputs section and Table IV.
Specifications subject to change without notice.
ORDERING GUIDE
Model
Package Description
Package Option
ADE7752AR
EVAL-ADE7752EB
SOIC Package
ADE7752 Evaluation
Board
R-24
(V
DD
= 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz,
T
MIN
to T
MAX
= –40 C to +85 C)
F1
F2
CF
t1
t6
t2
t3
t4
t5
Figure 1. Timing Diagram for Frequency Outputs
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