參數(shù)資料
型號(hào)： ADDI7100BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/20頁(yè)
文件大小： 0K
描述： IC PROCESSOR CCD SIGNAL7 32LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
應(yīng)用： 數(shù)碼相機(jī)
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤(pán)
ADDI7100
Rev. C | Page 15 of 20
INITIAL POWER-ON SEQUENCE
After power-on, the ADDI7100 automatically resets all internal
registers to default values. Settling of the internal voltage refer-
ence takes approximately 1 ms to complete. During this time,
normal clock signals and serial write operations can take place,
but valid output data do not occur until the reference is fully
settled. When loading the desired register settings, the STARTUP
register (Address 0x05[1:0]) must be set to 0x3.
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 15, a single ground plane is recommended
for the ADDI7100. This ground plane should be as continuous
as possible to ensure that all analog decoupling capacitors
provide the lowest possible impedance path between the power
and bypass pins and their respective ground pins. Place all
decoupling capacitors as close as possible to the package pins.
A single clean power supply is recommended for the ADDI7100,
but a separate digital driver supply can be used for DRVDD
(Pin 11). Always decouple DRVDD to DRVSS (Pin 12), which
should be connected to the analog ground plane. The advantages
of using a separate digital driver supply include using a lower
voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing
digital power dissipation and potential noise coupling. If the
digital outputs must drive a load larger than 20 pF, buffering is
the recommended method to reduce digital code transition
noise. Alternatively, placing series resistors close to the digital
output pins may also help to reduce noise.
Note that the exposed pad on the bottom of the package should
be soldered to the ground plane of the printed circuit board.
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