參數(shù)資料
型號: ADCMP609BRMZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 1/12頁
文件大?。?/td> 0K
描述: IC COMPARATOR TTL/CMOS 8-MSOP
標(biāo)準(zhǔn)包裝: 1
類型: 通用
元件數(shù): 1
輸出類型: CMOS,滿擺幅,TTL
電壓 - 電源,單路/雙路(±): 2.5 V ~ 5.5 V
電壓 - 輸入偏移(最小值): 3mV @ 2.5V
電流 - 輸入偏壓(最小值): 0.4µA @ 2.5V
電流 - 輸出(標(biāo)準(zhǔn)): 50mA
電流 - 靜態(tài)(最大值): 1.1mA
CMRR, PSRR(標(biāo)準(zhǔn)): 50dB CMRR,50dB PSRR
傳輸延遲(最大): 60ns
磁滯: 100µV
工作溫度: -40°C ~ 125°C
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
安裝類型: 表面貼裝
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 765 (CN2011-ZH PDF)
其它名稱: ADCMP609BRMZ-REEL7DKR
Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparator
ADCMP609
Rev. A
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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
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FEATURES
Fully specified rail-to-rail at VCC = 2.5 V to 5.5 V
Input common-mode voltage from 0.2 V to VCC + 0.2 V
Low glitch TTL-/CMOS-compatible output stage
40 ns propagation delay
Low power 1 mW at 2.5 V
Shutdown pin
Programmable hysteresis
Power supply rejection > 60 dB
40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
FUNCTIONAL BLOCK DIAGRAM
06
91
8-
0
01
ADCMP609
NONINVERTING
INPUT
INVERTING
INPUT
Q OUTPUT
+
SDN
Figure 1.
GENERAL DESCRIPTION
The ADCMP609 is a fast comparator fabricated on XFCB2, an
Analog Devices, Inc., proprietary process. These comparators
are exceptionally versatile and easy to use. Features include an
input range from VEE 0.2 V to VCC + 0.2 V, low noise, TTL-
/CMOS-compatible output drivers, and adjustable hysteresis
and/or shutdown inputs.
The device offers 40 ns propagation delay driving a 15 pF load
with 10 mV overdrive on 500 μA typical supply current.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a 0.2 V to +3.0 V
input signal range up to a +5.5 V positive supply with a 0.2 V
to +5.7 V input signal range.
The TTL-/CMOS-compatible output stage is designed to drive
up to 15 pF with full rated timing specifications and to degrade
in a graceful and linear fashion as additional capacitance is added.
The input stage of the comparator offers robust protection against
large input overdrive, and the outputs do not phase reverse when
the valid input signal range is exceeded. A programmable hysteresis
feature is also provided.
The ADCMP609, available in an 8-lead MSOP package, features
a shutdown pin and hysteresis control.
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