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參數(shù)資料
| 型號： | ADCMP605BCPZ-WP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP TTL/CMOS 1CHAN 12LFCSP |
| 標準包裝： | 50 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補充型，LVDS，滿擺幅 |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 3V |
| 電流 - 輸入偏壓（最小值）： | 5µA @ 3V |
| 電流 - 輸出（標準）： | 50mA |
| 電流 - 靜態(tài)（最大值）： | 3mA |
| CMRR, PSRR（標準）： | 50dB CMRR，50dB PSRR |
| 傳輸延遲（最大）： | 3ns |
| 磁滯： | 100µV |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 12-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 托盤 - 晶粒 |
ADCMP604/ADCMP605
Rev. A | Page 12 of 16
The hysteresis control pin appears as a 1.25 V bias voltage
seen through a series resistance of 70 kΩ ± 20% throughout the
hysteresis control range. The advantages of applying hysteresis
in this manner are improved accuracy, improved stability, reduced
component count, and maximum versatility. An external bypass
capacitor is not recommended on the HYS pin because it would
likely degrade the jitter performance of the device and impair the
latch function. As described in the Using/Disabling the Latch
Feature section, hysteresis control need not compromise the
latch function.
0
50
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250
50
100
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500
HYSTERESIS RESISTOR (k)
H
Y
ST
E
R
ES
IS
(
m
V
)
VCC = 2.5V
VCC = 5.5V
05
91
6-
0
26
Figure 20. Hysteresis vs. RHYS Control Resistor
CROSSOVER BIAS POINTS
Rail-to-rail inputs of this type, in both op amps and comparators,
have a dual front-end design. Certain devices are active near
the VCCI rail and others are active near the VEE rail. At some pre-
determined point in the common-mode range, a crossover
occurs. At this point, normally VCCI/2, the direction of the bias
current reverses and there are changes in measured offset
voltages and currents.
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PCB design
practice, as discussed in the Optimizing Performance section,
these comparators should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the violent chattering seen with most other high
speed comparators. With additional capacitive loading or poor
bypassing, oscillation is observed. This oscillation is due to the
high gain bandwidth of the comparator in combination with
feedback parasitics in the package and PCB. In many applications,
chattering is not harmful.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCMP605BCPZ-WP1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP606 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators |
| ADCMP606_0610 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators |
| ADCMP606_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators |
| ADCMP606BKSZ-R2 | 功能描述:IC COMP TTL/CMOS 1CHAN SC70-6 RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:帶電壓基準 元件數(shù):4 輸出類型:開路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標準）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產(chǎn)品目錄頁面:1386 (CN2011-ZH PDF) |
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