參數(shù)資料
型號(hào): ADCMP552BRQZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 14/16頁(yè)
文件大?。?/td> 0K
描述: IC COMPARATOR PECL/LVPECL 20QSOP
標(biāo)準(zhǔn)包裝: 56
類型: 帶鎖銷
元件數(shù): 1
輸出類型: 補(bǔ)充型,差分,LVPECL,開(kāi)路發(fā)射極,PECL
電壓 - 電源,單路/雙路(±): 3.14 V ~ 5.25 V
電壓 - 輸入偏移(最小值): 10mV @ 3.3V
電流 - 輸入偏壓(最小值): 28µA @ 3.3V
電流 - 輸出(標(biāo)準(zhǔn)): 55mA @ 3.3V
電流 - 靜態(tài)(最大值): 17mA
CMRR, PSRR(標(biāo)準(zhǔn)): 76dB CMRR,75dB PSRR
傳輸延遲(最大): 0.625ns
磁滯: ± 0.5mV
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SSOP(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 管件
產(chǎn)品目錄頁(yè)面: 764 (CN2011-ZH PDF)
配用: EVAL-ADCMP552BRQZ-ND - BOARD EVALUATION ADCMP552BRQZ
Data Sheet
ADCMP551/ADCMP552/ADCMP553
Rev. A | Page 7 of 16
Pin No.
Mnemonic
Function
ADCMP551
ADCMP552
ADCMP553
12
15
LEB
One of Two Complementary Inputs for Channel B Latch Enable. In the compare
mode (logic low), the output tracks changes at the input of the comparator. In
the latch mode (logic high), the output reflects the input state just prior to the
comparator’s being placed in the latch mode. LEB must be driven in conjunction
with LEB.
13
16
LEB
One of Two Complementary Inputs for Channel B Latch Enable. In the compare
mode (logic low), the output tracks changes at the input of the comparator. In
the latch mode (logic high), the output reflects the input state just prior to the
comparator’s being placed in the latch mode. LEB must be driven in conjunction
with LEB.
15
18
QB
One of Two Complementary Outputs for Channel B. QB is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEB for more information.
16
19
QB
One of Two Complementary Outputs for Channel B. QB is logic high if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEB for more information.
7
VCC
Positive Supply Terminal.
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