參數(shù)資料
型號: ADCMP552BRQ
廠商: Analog Devices Inc
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC COMPARATOR PECL/LVPECL 20QSOP
標(biāo)準(zhǔn)包裝: 56
類型: 帶鎖銷
元件數(shù): 1
輸出類型: 補(bǔ)充型,差分,LVPECL,開路發(fā)射極,PECL
電壓 - 電源,單路/雙路(±): 3.14 V ~ 5.25 V
電壓 - 輸入偏移(最小值): 10mV @ 3.3V
電流 - 輸入偏壓(最小值): 28µA @ 3.3V
電流 - 輸出(標(biāo)準(zhǔn)): 55mA @ 3.3V
電流 - 靜態(tài)(最大值): 17mA
CMRR, PSRR(標(biāo)準(zhǔn)): 76dB CMRR,75dB PSRR
傳輸延遲(最大): 0.625ns
磁滯: ± 0.5mV
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SSOP(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 管件
配用: EVAL-ADCMP552BRQZ-ND - BOARD EVALUATION ADCMP552BRQZ
ADCMP551/ADCMP552/ADCMP553
Data Sheet
Rev. A | Page 10 of 16
TIMING INFORMATION
Figure 17. System Timing Diagram
Figure 17 shows the compare and latch features of the ADCMP55x family. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol
Timing
Description
tPDH
Input to Output High Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition
tPDL
Input to Output Low Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition
tPLOH
Latch Enable to Output High Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition
tPLOL
Latch Enable to Output Low Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition
tH
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs
tPL
Minimum Latch Enable Pulse Width
Minimum time the latch enable signal must be high to acquire an input signal change
tS
Minimum Setup Time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs
tR
Output Rise Time
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points
tF
Output Fall Time
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points
VOD
Voltage Overdrive
Difference between the differential input and reference input voltages
50%
VREF ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VIN
VOD
tS
tPL
04722-016
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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