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參數(shù)資料
| 型號： | ADC71AG |
| 英文描述： | 16-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位模擬數(shù)字轉換器 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 96K |
| 代理商： | ADC71AG |
2
ADC71
SPECIFICATIONS
ELECTRICAL
At +25
°
C and rated power supplies, unless otherwise noted.
ADC71J, K
ADC71A, B
MODEL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
RESOLUTION
16
16
Bits
INPUTS
ANALOG
Voltage Ranges: Bipolar
±
2.5,
±
5,
±
10
0 to +5, 0 to +10,
0 to +20
±
2.5,
±
5,
±
10
0 to +5, 0 to +10,
0 to +20
V
V
Unipolar
Input Impedance (Direct Input)
0 to +5V,
±
2.5V
0 to +10V,
±
5.0V
0 to +20V,
±
10V
DIGITAL
(1)
2.5
5
10
2.5
5
10
k
k
k
Convert Command Positive pulse 50ns wide (min) trailing edge (“1” to “0” initiates conversion)
1
Logic Loading
TTL Load
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error
(2)
Offset
(2)
: Unipolar
Bipolar
Linearity Error: K, B
J, A
Inherent Quantization Error
Differential Linearity Error
±
0.1
±
0.05
±
0.1
±
0.2
±
0.1
±
0.2
±
0.003
±
0.006
±
0.1
±
0.05
±
0.1
±
0.2
±
0.1
±
0.2
±
0.003
±
0.006
%
% of FSR
(3)
% of FSR
% of FSR
% of FSR
LSB
% of FSR
±
1/2
±
0.003
±
1/2
±
0.003
POWER SUPPLY SENSITIVITY
±
15VDC
+5VDC
0.003
0.001
0.003
0.001
% of FSR/%V
S
% of FSR/%V
S
CONVERSION TIME
(4)
14 Bits
50
50
μ
s
min
WARM-UP TIME
5
*
DRIFT
Gain
Offset: Unipolar
Bipolar
Linearity
No Missing Codes Temp Range
J, A (13 Bits)
K, B (14 Bits)
±
10
±
2
±
8
±
2
±
15
±
4
±
10
±
3
*
*
ppm/
°
C
±
2
±
10
±
2
ppm of FSR/
°
C
ppm of FSR/
°
C
ppm of FSR/
°
C
±
5
0
0
+70
+70
–25
–25
+85
+85
°
C
°
C
OUTPUT
DIGITAL DATA
(All Codes Complementary)
Parallel Output Codes
(5)
: Unipolar
CSB
Bipolar
COB, CTC
(6)
Output Drive
Serial Data Code (NRZ)
Output Drive
Status
Status Output Drive
Clock Output Drive
Frequency
(7)
2
*
TTL Loads
CSB, COB
2
*
TTL Loads
Logic “1” During Conversion
2
2
2
2
TTL Loads
TTL Loads
kHz
280
*
INTERNAL REFERENCE VOLTAGE
Max External Current with
No Degradation of Specs
Temp Coefficient
6.0
6.3
6.6
6.0
6.3
6.6
V
±
200
±
10
±
200
*
μ
A
ppm/
°
C
POWER SUPPLY REQUIREMENTS
Power Consumption
Rated Voltage, Analog
Rated Voltage, Digital
Supply Drain +15VDC
Supply Drain –15VDC
Supply Drain +5VDC
655
±
15
+5
+10
–28
+17
655
*
*
*
*
*
mW
VDC
VDC
mA
mA
mA
±
11.4
+4.75
±
16
+4.75
+15
–35
+20
*
*
*
*
*
*
*
TEMPERATURE RANGE
Specification
Operating (Derated Specs)
Storage
0
+70
+85
+125
–25
–55
–55
+85
+125
+125
°
C
°
C
°
C
–25
–55
NOTES: (1) CMOS/TTL compatible, i.e., Logic “0” = 0.8V, max Logic “1” = 2.0V, min for inputs. For digital outputs Logic “0” = +0.4V, max Logic “1” = 2.4V min.
(2) Adjustable to zero. (3) FSR means Full Scale Range. For example, unit connected for
±
10V range has 20V FSR. (4) Conversion time may be shortened with
“Short Cycle” set for lower resolution, see “Additional Connections Required” section. (5) See Table I. CSB = Complementary Straight Binary. COB = Complementary
Offset Binary. CTC = Complementary Two’s Complement. (6) CTC coding obtained by inverting MSB (Pin 1).
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