參數(shù)資料
型號： ADC1006S055H
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Single 10 bits ADC up to 55 Msps
封裝： ADC1006S055H/C1<SOT307-2 (QFP44)|<<http://www.nxp.com/packages/SOT307-2.html<1<Always Pb-free,;ADC1006S055H/C1<SOT307-2 (QFP44)|<<http://www.nxp.com/packages/SOT307-2.htm
文件頁數(shù)： 11/31頁
文件大?。?/td> 384K
代理商： ADC1006S055H
ADC1006S055_070_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 12 August 2008
11 of 31
NXP Semiconductors
ADC1006S055/070
Single 10 bits ADC, up to 55 MHz or 70 MHz
[1]
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2]
The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC level vary 1 : 1 with V
CCD
) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC level vary 1 : 1 with V
CCD
) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC level vary 1 : 1 with V
CCD
) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling
takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF
capacitor.
e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has
to be connected to the ground.
[3]
The ADC input range can be adjusted with an external reference connected to VREF pin. This voltage has to be referenced to V
CCA
;
see
Figure 12
.
[4]
The
3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[5]
Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics:
where
α
1H
is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see
Figure 6
.
Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see
Figure 8
.
[6]
[7]
Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up
to half of the clock frequency (Nyquist frequency). Conversion to SIgnal-to_Noise_Distortion ratio (SINAD) is given by
SINAD = ENOB
×
6.02 + 1.76 dB; see
Figure 5
.
[8]
Intermodulation measured relative to either tone with analog input frequencies of 20 MHz and 20.1 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter (
6 dB below full scale for each input signal).
IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product.
[9]
Output data acquisition: the output data is available after the maximum delay of t
d(o)
; see
Figure 3
.
Timing (C
L
= 10 pF)
[9]
t
d(s)
t
h(o)
t
d(o)
3-state output delay times; see
Figure 4
t
dZH
float to active HIGH
delay time
t
dZL
float to active LOW
delay time
t
dHZ
active HIGH to float
delay time
t
dLZ
active LOW to float
delay time
sampling delay time
output hold time
output delay time
C
C
C
-
4
-
0.25
6.4
9.0
1
-
13
ns
ns
ns
C
-
5.1
9.0
ns
C
-
7.0
11
ns
C
-
9.7
14
ns
C
-
9.5
13
ns
Table 6.
V
CCA
= V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; V
CCD
= V37 to V38 and V15 to V17 = 4.75 V to 5.25 V;
V
CCO
= V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; T
amb
=
40
°
C to +85
°
C;
V
I(IN)(p-p)
V
I(INN)(p-p)
= 1.9 V; V
VREF
= V
CCA3
1.75 V; V
I(cm)
= V
CCA3
1.6 V; typical values measured at V
CCA
= V
CCD
= 5 V
and V
CCO
= 3.3 V T
amb
= 25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Test
[1]
Min
Typ
Max
Unit
THD
20 log
α
---------------------------------------------------------------------------------------------------------------------------------------
(
)
2
α
(
)
2
α
a
1H
(
)
2
α
( )
2
α
(
)
2
+
+
+
+
(
)
=
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADC1006S055H/C1,51 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 10BIT ADC 55MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADC1006S055H/C1,518 制造商:NXP Semiconductors 功能描述:
ADC1006S055H/C1,55 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC ADC 10BIT PAR 55MHZ RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADC1006S055H/C1,551 制造商:NXP Semiconductors 功能描述:
ADC1006S055H/C1-T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 10BIT ADC 55MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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