參數(shù)資料
型號(hào)： ADC1003S030TS
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Single 10 bits ADC up to 30 Msps, with voltage regulator
封裝： ADC1003S030TS/C1<SOT341-1 (SSOP28)|<<http://www.nxp.com/packages/SOT341-1.html<1<Always Pb-free,;ADC1003S030TS/C1<SOT341-1 (SSOP28)|<<http://www.nxp.com/packages/SOT341-1
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 135K
代理商： ADC1003S030TS
ADC1003S030_040_050_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 7 August 2008
9 of 20
NXP Semiconductors
ADC1003S030/040/050
Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage
regulator
[1]
In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less
than 0.5 ns
[2]
Analog input voltages producing code 0 up to and including code 1023:
a) V
offset
BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
(V
RB
) at T
amb
= 25
°
C.
b) V
offset
TOP is the difference between reference voltage on pin RT (V
RT
) and the analog input which produces data outputs equal to
code 1023 at T
amb
= 25
°
C.
In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter
reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins RB and RT via offset resistors
R
OB
and R
OT
as shown in
Figure 3
.
V
V
–
OB
L
[3]
a) The current flowing into the resistor ladder is
and the full-scale input range at the converter
to cover code 0 to code 1023, is
b) Since R
L
, R
OB
and R
OT
have similar behavior with respect to process and temperature variation, the ratio
will
be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends
mainly on the difference V
RT
V
RB
and its variation with temperature and supply voltage. When several ADCs are connected in
parallel and fed with the same reference source, the matching between each of them is optimized.
[4]
[5]
The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 2 LSB, neither any significant attenuation are observed in the reconstructed signal.
[6]
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
Differential phase
[9]
dif
differential phase
f
clk
= 40 MHz;
PAL modulated ramp
-
0.4
-
deg
Timing (f
clk
= 40 MHz; C
L
= 15 pF); see
Figure 4
[10]
t
d(s)
sampling delay time
t
h(o)
output hold time
t
d(o)
output delay time
-
4
-
-
-
3
-
10
12
-
-
-
13
15
15
ns
ns
ns
ns
pF
V
CCO
= 4.75 V
V
CCO
= 3.15 V
C
L
3-state output delay times; see
Figure 5
t
dZH
float to active HIGH delay
time
t
dZL
float to active LOW delay
time
t
dHZ
active HIGH to float delay
time
t
dLZ
active LOW to float delay
time
load capacitance
-
5.5
8.5
ns
-
12
15
ns
-
19
24
ns
-
12
15
ns
Table 6.
V
CCA
= V3 to V4 = 4.75 V to 5.25 V; V
CCD
= V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
V
CCO
= V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; T
amb
= 0
°
C to 70
°
C; typical values measured at
V
CCA
= V
CCD
= 5 V and V
CCO
= 3.3 V; C
L
= 15 pF and T
amb
= 25
°
C; unless otherwise specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Min
Typ
Max
Unit
I
L
OT
----------------------------------------
=
V
I
R
L
I
L
×
R
R
L
R
OB
R
OT
+
+
----------------------------------------
V
RT
V
RB
–
(
)
×
0.848
V
RT
V
RB
–
(
)
×
=
=
=
R
R
L
R
OB
R
OT
+
+
----------------------------------------
E
G
V
--------------------------------------------------------
V
–
V
i
P
(
P
–
)
P
–
(
)
100
×
=
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