參數(shù)資料
型號: ADC-207MC
廠商: MURATA POWER SOLUTIONS INC
元件分類: ADC
中文描述: 1-CH 7-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP18
封裝: ROHS COMPLIANT, CERAMIC, DIP-18
文件頁數(shù): 2/6頁
文件大小: 210K
代理商: ADC-207MC
PHYSICAL/ENVIRONMENTAL
MIN.
PARAMETERS
Operating Temp. Range, Case:
LC/MC Versions
MM/LM/QL Versions
Storage Temp. Range
Package Type
DIP
LCC
TYP
MAX.
UNITS
0
+70
+125
+150
°C
°C
°C
–55
–65
18-pin ceramic DIP
24-pin ceramic LCC
Functional Specifications
(Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V
–REFERENCE = ground, unless noted)
ANALOG INPUT
Input Type
Input Range
(dc-20MHz)
Input Impedance
Input Capacitance
(Full Range)
MIN.
0
TYP.
Single-ended, non-isolated
+5
1000
10
MAX.
UNITS
Volts
Ohms
pF
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Sample Pulse Width
(During Sampling Portion of Clock)
Reference Ladder Resistance
+3.2
±1
±1
+0.8
±5
±5
Volts
Volts
microamps
microamps
12
225
330
ns
Ohms
PERFORMANCE
20
Conversion Rate
Harmonic Distortion
(8MHz 2nd Order Harmonic)
Differential Gain
Differential Phase
Aperture Delay
Aperture Jitter
No Missing Codes
LC/MC grade
LM/MM grade
Integral Linearity
Over Temperature Range
Differential Nonlinearity
Over Temperature Range
Power Supply Rejection
25
MHz
–40
3
1.5
8
50
dB
%
degrees
ns
ps
0
±0.8
±1
±0.3
±0.4
±0.02
+70
+125
±1
±0.5
±0.6
°C
°C
LSB
LSB
LSB
LSB
–55
%FSR/%Vs
DIGITAL OUTPUTS
Data Coding
Data Output Resolution
Logic Levels
Logic "1"
Logic "0" (at 1.6mA)
Logic Loading "1"
Logic Loading "0"
Output Data Valid Delay
(From Rising Edge)
Straight binary
7
Bits
+2.4
–4
+4
+4.5
+0.4
Volts
Volts
mA
mA
15
17
ns
POWER REQUIREMENTS
+3.0
Power Supply Range
(+V
DD
)
Power Supply Current
Power Dissipation
Footnotes:
At full power input and chip selects enabled.
At 4MHz input and 20MHz clock.
For 10-step, 40 IRE NTSC ramp test.
Adjustable using reference ladder midpoint tap. See ADC-207 Operation.
+5.0
+50
250
+5.5
+70
385
Volts
mA
mW
(MSB)
0.1μF
0.1μF
4.7μF
0.01μF
+5V
+15
+
+
–15
47μF
11
12
10
5
HA-5033
10
+5V
20MHz
CLOCK
(LSB)
B7
B6
B5
B4
B3
B2
B1
OF
OF
B1
B2
B3
B4
B5
B6
B7
+V
DD
CS2
CS1
+REFERENCE
MID
V
IN
–REFERENCE
DIGITAL GND
ANALOG GND
CLOCK
18
1
2
3
4
5
6
7
8
9
0.1μF
+
47μF
17
16
15
14
13
12
11
10
PARAMETERS
Power Supply Voltage (+VDD)
Digital Inputs
Analog Input
Reference Inputs
Digital Outputs
(short circuit protected to ground)
Lead Temperature (10 sec. max.)
LIMITS
–0.5 to +7
–0.5 to +5.5
–0.5 to (+VDD +0.5)
–0.5 to +VDD
–0.5 to +5.5
UNITS
Volts
Volts
Volts
Volts
Volts
+300
°C
ABSOLUTE MAXIMUM RATINGS
Figure 2. Typical Connections for Using the ADC-207
TECHNICAL NOTES
1.
Input Buffer Amplifier – Since the ADC-207 has a switched capacitor type input, the input
impedance of the 207 is dependent on the clock frequency. At relatively slow conversion rates,
a general purpose type input buffer can be used; at high conversion rates DATEL recommends
either the HA-5033 or Elantec 2003. See Figure 2 for typical connections.
2. Reference Ladder – Adjusting the voltage at +REFERENCE adjusts the gain of the ADC-207.
Adjusting the voltage at –REFERENCE adjusts the offset or zero of the ADC-207. The midpoint
pin is usually bypassed to ground through a 0.1μF capacitor, although it can be tied to a precision
voltage halfway between +REFERENCE and –REFERENCE. This would improve integral linearity
beyond 7 bits.
3.
Clock Pulse Wdth – To improve performance at Nyquist bandwidths, the clock duty cycle can
be adjusted so that the low portion of the clock pulse is 12ns wide. The smaller aperture allows
the ADC-207 to closely resemble an ideal sampler. See Figure 4.
4. At sampling rates less than 100kHz, there may be some degradation in offset and differential
nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing the
time spent in the sample mode).
CAUTION
Since the ADC-207 is a CMOS device, normal precautions against static electricity should be
taken. Use ground straps, grounded mats, etc. The Absolute Maximum Ratings of the device
MUST NOT BE EXCEEDED as irrevocable damage to the ADC-207 will occur.
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