參數(shù)資料
型號(hào)： ADAV803
廠商： Analog Devices, Inc.
元件分類(lèi)： Codec
英文描述： Audio Codec for Recordable DVD
中文描述： 音頻編解碼器可刻錄DVD
文件頁(yè)數(shù)： 21/56頁(yè)
文件大?。?/td> 906K
代理商： ADAV803
ADAV803
The number of inp
FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay
register. This feature is useful in varispeed applications to
prevent the read pointer to the FIFO from running ahead of the
write pointer. When set, Bit 7 of the group delay and mute-in
register soft-mutes the sample rate. Increasing the offset of the
write address pointer is useful for applications in which small
changes in the sample rate ratio between f
S_IN
and f
S_OUT
are
expected. The maximum decimation rate can be calculated
from the RAM word depth and the group delay as
Rev. 0 | Page 21 of 56
ut samples added to the write pointer of the
(512 16)/64 taps = 7.75
e integer output
e
utput by the ratio of f
S_IN
/f
S_OUT
en f
S_IN
> f
S_OUT
.
for short group delay and
(512 64)/64 taps = 7
for long group delay.
The digital servo loop is essentially a ramp filter that provides
the initial pointer to the address in RAM and ROM for the start
of the FIR convolution. The RAM pointer is th
of the ramp filter, and the ROM is the fractional part. The
digital servo loop must provide excellent rejection of jitter on
the f
S_IN
and f
S_OUT
clocks, as well as measure the arrival of th
f
S_OUT
clock within 4.97 ps. The digital servo loop also divides
the fractional part of the ramp o
to dynamically alter the ROM coefficients wh
0
D
S
)
I
I
REG 0x00
BITS 1–0
REG 0x76
BIT 0
REG 0x76
BIT 1
REG 0x62
BITS 7–6
D
S
)
DIR
PLAYBACK
AUXILIARY IN
ADC
M
X
SRC
MCLK
SRC
OUTPUT
SRC
SRC
INPUT
P
P
Figure 33. Clock and Datapath Control on the SCR
The digital servo loop is implemented with a multirate filter. To
settle the digital servo loop filter more quickly upon startup or a
change in the sample rate, a fast mode has been added to the
filter. When the digital servo loop starts up or the sample rate is
changed, the digital servo loop enters fast mode to adjust and
settle on the new sample rate. Upon sensing that the digital
ervo
serv loop returns to n
own to reasonable value,
ormal
(or slow) mo
de.
in
E
it in the sam le rate error
that clicks or pops might
ser know
egiste
be present in the digital audio data. The output of the SRC can
be muted by asserting Bit 7 of the group delay and mute
until the SRC has changed to slow mode. The MUTE_OUT bit
can be set to generate an interrupt when the SRC changes to
slow mode, indicating that the data is being sample rate
converted accurately.
to let the u
register
de
64 taps when f
S_IN
>
f
starting address of the RAM address pointer and the ROM
address pointer from the digital servo loop at the start of the
f
S_OUT
period. The FIR filter then steps through the RAM by
decrementing its address by 1 for each tap, and the ROM
pointer increments its address by the (f
S_OUT
/f
S_IN
) × 2
20
ratio for
. The FIR filter performs its convolution by loading in the
S_OUT
f
S_IN
> f
S_OUT
or 2
20
for f
S_OUT
≥ f
S_IN
. Once the ROM address rolls
over, the convolution is completed.
s
loop is settling d
a
the digital
Dur g fast mode, the MUT _OUT b
r
r is asserted
p
The frequency responses of the digital servo loop for fast mo
and slow mode are shown in Figure 34. The FIR filter is a 64-tap
filter when f
S_OUT
≥ f
S_IN
and is (f
S_IN
/f
S_OUT
) ×
0
FREQUENCY (Hz)
M
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
0.01
0.1
1
10
100
1k
10k
100k
SLOW MODE
FAST MODE
–220
Figure 34. Frequency Response of the Digital Servo Loop. f
S_IN
is the X-Axis,
f
S_OUT
= 192 KHz, Master Clock is 30 MHz
The convolution is performed for both the left and right
channels, and the multiply accumulate circuit used for the
convolution is shared between the channels. The f
S_IN
/f
S_OUT
sample rate ratio circuit is used to dynamically alter the
coefficients in the ROM when f
S_IN
> f
S_OUT
. The ratio is
calculated by comparing the output of an f
S_OUT
counter to the
output of an f
S_IN
counter. If f
S_OUT
> f
S_IN
, the ratio is held at one.
If f
S_IN
> f
S_OUT
, the sample rate ratio is updated, if it is different
by more than two f
S_OUT
periods from the previous f
S_OUT
to f
S_IN
comparison. This is done to provide some hysteresis to prevent
the filter length from oscillating and causing distortion.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADAV803AST 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk
ADAV803ASTZ 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
ADAV803ASTZ-REEL 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類(lèi)型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
ADAV804AST 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk
ADAV804ASTZ 制造商:Analog Devices 功能描述:
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