ADAV4601
Rev. B | Page 23 of 60
I2S DIGITAL AUDIO OUTPUTS
One I2S output, SDO0, uses the same serial clocks as the serial
inputs, which are BCLK1 and LRCLK1 by default. If an additional
digital output is required, an additional pin can be reconfigured
as a serial digital output, as shown in
Figure 34.
SDO0
R
L
R
L
S/PDIF
OUTPUT
SPDIF_OUT (SDO1)
0
70
-0
27
I2S OUTPUT
INTERFACE
BCLK1
LRCLK1
Figure 34. I2S Digital Outputs
S/PDIF INPUT/OUTPUT
The S/PDIF output (SPDIF_OUT/SDO1) uses a multiplexer
to select an output from the audio processor or to pass through
the unprocessed SPDIF_IN signals, as shown in
Figure 35. On
the ADAV4601, the S/PDIF inputs, SPDIF_IN0/SPDIF_IN1/
SPDIF_IN2/SPDIF_IN3/SPDIF_IN4/SPDIF_IN5/SPDIF_IN6,
are available on the SDIN3, LRCLK0, BCLK0, LRCLK1, BCLK1,
LRCLK2, and BCLK2 pins, respectively. It is possible to have all
seven S/PDIF inputs connected to different S/PDIF signals at one
time. A consequence of this setup is that none of the LRCLKs and
BCLKs are available for use with the digital inputs SDIN0, SDIN1,
SDIN2, and SDIN3. If there is only one S/PDIF input in use, using
the SDIN3 pin as the dedicated S/PDIF input is recommended; this
enables BCLK0/LRCLK0, BCLK1/LRCLK1, and BCLK2/LRCLK2
to be used as the clock and framing signals for the synchronous
and asynchronous port. If SDIN3 is used as an S/PDIF input, it
should not be used internally as an input to the audio processor
because it contains invalid data. Similarly, if BCLK or LRCLK is
used as the S/PDIF input, they can no longer be used as the lock
and framing signals for SDIN0, SDIN1, SDIN2, and SDIN3. The
S/PDIF encoder supports only consumer formats that conform to
IEC-600958.
SDIN3 (SPDIF_IN0)
LRCLK0 (SPDIF_IN1)
BCLK0 (SPDIF_IN2)
LRCLK1 (SPDIF_IN3)
BCLK1 (SPDIF_IN4)
LRCLK2 (SPDIF_IN5)
BCLK2 (SPDIF_IN6)
SDO1 (SPDIF_OUT)
S/PDIF
ENCODER
07
0-
0
28
Figure 35. S/PDIF Output
HARDWARE MUTE CONTROL
The ADAV4601 mute input can be used to mute any of the
analog or digital outputs. When the MUTE pin goes low, the
selected outputs ramp to a muted condition. Unmuting is
handled in one of two ways and depends on the register setting.
By default, the MUTE pin going high causes the outputs to
immediately ramp to an unmuted state. However, it is also
possible to have the unmute operation controlled by a control
register bit. In this scenario, even if the MUTE pin goes high,
the device does not unmute until a bit in the control register is set.
This can be used when the user wants to keep the outputs
muted, even after the pin has gone high again, for example, in
the case of a fault condition. This allows the system controller
total control over the unmute operation.
AUDIO PROCESSOR
The internal audio processor runs at 2560 × fS; at 48 kHz, this is
122.88 MHz. Internally, the word size is 28 bits, which allows
24 dB of headroom for internal processing. Designed specifically
with audio processing in mind, it can implement complex audio
algorithms efficiently.
By default, the ADAV4601 loads a default audio flow, as shown
in
Figure 48. However, because the audio processor is fully
programmable, a custom audio flow can be quickly developed
and loaded to the audio processor.
The audio flow is contained in program RAM and parameter
RAM. Program RAM contains the instructions to be processed by
the audio processor, and parameter RAM contains the coefficients
that control the flow, such as volume control, filter coefficients,
and enable bits.
GRAPHICAL PROGRAMMING ENVIRONMENT
Custom flows for the ADAV4601 are created in a powerful drag-
and-drop graphical programming application called SigmaStudio.
No knowledge of assembly code is required to program the
ADAV4601. Featuring a comprehensive library of audio processing
blocks (such as filters, delays, dynamics processors, and third-party
algorithms), sigma studio allows a quick and simple creation of
custom flows. For debugging purposes, run-time control of the
audio flow allows the user to fully configure and test the created
flow.
07
0-
1
09
Figure 36. SigmaStudio Window