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參數(shù)資料
| 型號： | ADAV400KSTZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Audio Codec with Embedded SigmaDSP Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO80 |
| 封裝： | 14 X 14 MM, ROHS COMPLIANT, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 446K |
| 代理商： | ADAV400KSTZ-REEL |
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ADAV400
AUDIO CORE CONTROL REGISTER
The bits in this register control the operation of the DSP core of
the ADAV400 (see Table 29).
Rev. 0 | Page 31 of 36
Enable SDO2 and SDO3 (Bit 14)
This bit is set to 1 by default and can be used to disable SDO2
and SDO3 if required.
Slew RAM Muted (Bit 13)
This bit is set to 1 when the slew RAM mute operation has been
completed. This bit is read-only and is automatically cleared
by reading.
Write Zero to Target RAM (Bit 12)
Setting this bit to 1 is equivalent to writing 0s to all locations in
the target RAM. This effectively mutes any slew RAMs, such as
volume controls used in a signal flow. To enable normal
operation, clear this bit to 0.
Clear Registers to All Zeros (Bit 9)
Setting this bit to 0 sets the contents of the accumulators and
serial output registers to 0. This bit defaults to 0; therefore, the
ADAV400 powers up in clear mode and does not pass signals
until a 1 is written to this bit. This is intended to prevent noises
from inadvertently occurring during the power-up sequence.
Force Multiplier to Zero (Bit 8)
When this bit is set to 1, the input to the DSP multiplier is set to
0, which results in the multiplier output being 0. This control bit
is included for maximum flexibility and is normally not used.
Initialize Data Memory with Zeros (Bit 7)
Setting this bit to 1 initializes all data memory locations to 0.
This bit is cleared to 0 after the operation is complete. Assert
this bit after a complete program/parameter download has
occurred to ensure click-free operation.
Zero Serial Input Port (Bit 6)
When this bit is set to 1, all input channels to the DSP core are
forced to all 0s, effectively muting the output.
Initiate Safe Transfer to Target RAM (Bit 5)
Setting this bit to 1 initiates a safeload transfer to the target/slew
RAM. This bit clears when the operation is complete. Of five
safeload register pairs (address/data), only those registers that have
been written since the last safeload event occurred are transferred.
Address 0 corresponds to the first target RAM location.
Initiate Safe Transfer to Parameter RAM (Bit 4)
Setting this bit to 1 initiates a safeload transfer to the parameter
RAM. This bit clears when the operation is complete. Of five
safeload registers pairs (address/data), only those registers that have
been written since the last safeload event occurred are transferred.
Address 0 corresponds to the first parameter RAM location.
Program Length (Bits [1:0])
96 kHz and 192 kHz Modes
These bits set the length of the internal program. The default
program length is 2560 instructions for f
S
= 48 kHz, but the
program length can be shortened by factors of 2 to accommodate
sample rates higher than 48 kHz. For f
S
= 96 kHz, set the
program length to 1280 (01), and for f
S
= 192 kHz, set the
length to 640 steps (10).
Note that this is only valid for digital inputs and outputs.
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