參數(shù)資料
型號(hào): ADA4937-1YCPZ-R7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 16/29頁(yè)
文件大小: 0K
描述: IC ADC DRIVER DIFF 16-LFCSP
設(shè)計(jì)資源: Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
標(biāo)準(zhǔn)包裝: 1
類型: ADC 驅(qū)動(dòng)器
應(yīng)用: 數(shù)據(jù)采集
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 781 (CN2011-ZH PDF)
其它名稱: ADA4937-1YCPZ-R7DKR
ADA4937-1/ADA4937-2
Data Sheet
Rev. D | Page 22 of 28
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4937-x is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design. This section shows a detailed example of how
the design issues of the ADA4937-1 were addressed.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4937-1 as possible.
However, the area near the feedback resistors (RF), input gain
resistors (RG), and the input summing nodes (Pin 2 and Pin 3)
should be cleared of all ground and power planes (see Figure 61).
Clearing the ground and power planes minimizes any stray capa-
citance at these nodes and prevents peaking of the response of
the amplifier at high frequencies.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7.
06
59
1-
08
6
Figure 61. Ground and Power Plane Voiding in Vicinity of RF and RG
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended that two parallel bypass capaci-
tors (1000 pF and 0.1 μF) be used for each supply with the 1000 pF
capacitor placed closer to the device; further away, provide low
frequency bypassing using 10 μF tantalum capacitors from each
supply to ground.
Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a sym-
metrical layout to maximize balanced performance. When
routing differential signals over a long distance, keep PCB
traces close together and twist any differential wiring to mini-
mize loop area. Doing this reduces radiated energy and makes
the circuit less susceptible to interference.
06
59
1-
087
1.30
0.80
1.30
Figure 62. Recommended PCB Thermal Attach Pad Dimensions (mm)
06
59
1-
08
8
0.30
PLATED
VIA HOLE
1.30
GROUND PLANE
POWER PLANE
BOTTOM METAL
TOP METAL
Figure 63. Cross-Section of 4-layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in mm)
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