參數(shù)資料
型號(hào)： AD9995KCPRL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC56
封裝： 8 X 8 MM, MO-220-VLLD-2, LFCSP-56
文件頁數(shù)： 51/60頁
文件大?。?/td> 1593K
代理商： AD9995KCPRL
AD9995
–51–
Table XL. V-Sequence 3 (VSEQ3) Register Map
Data Bit Default
Address Content
98
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Name
HBLKMASK_3
CLPOBPOL_3
PBLKPOL_3
VPATSEL_3
VMASK_3
HBLKALT_3
UNUSED
VPATREPO_3
VPATREPE_3
VPATSTART_3
HDLEN_3
PBLKTOG1_3
PBLKTOG2_3
HBLKTOG1_3
HBLKTOG2_3
HBLKTOG3_3
HBLKTOG4_3
HBLKTOG5_3
HBLKTOG6_3
CLPOBTOG1_3
CLPOBTOG2_3
Description
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 3
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
Enable HBLK Alternation
Unused
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 3
PBLK Toggle Position 1 for V-Sequence 3
PBLK Toggle Position 2 for V-Sequence 3
HBLK Toggle Position 1 for V-Sequence 3
HBLK Toggle Position 2 for V-Sequence 3
HBLK Toggle Position 3 for V-Sequence 3
HBLK Toggle Position 4 for V-Sequence 3
HBLK Toggle Position 5 for V-Sequence 3
HBLK Toggle Position 6 for V-Sequence 3
CLPOB Toggle Position 1 for V-Sequence 3
CLPOB Toggle Position 2 for V-Sequence 3
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
99
9A
9B
9C
9D
9E
9F
Table XLI. V-Sequence 4 (VSEQ4) Register Map
Data Bit Default
Address Content
A0
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Name
HBLKMASK_4
CLPOBPOL_4
PBLKPOL_4
VPATSEL_4
VMASK_4
HBLKALT_4
UNUSED
VPATREPO_4
VPATREPE_4
VPATSTART_4
HDLEN_4
PBLKTOG1_4
PBLKTOG2_4
HBLKTOG1_4
HBLKTOG2_4
HBLKTOG3_4
HBLKTOG4_4
HBLKTOG5_4
HBLKTOG6_4
CLPOBTOG1_4
CLPOBTOG2_4
Description
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 4
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
Enable HBLK Alternation
Unused
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 4
PBLK Toggle Position 1 for V-Sequence 4
PBLK Toggle Position 2 for V-Sequence 4
HBLK Toggle Position 1 for V-Sequence 4
HBLK Toggle Position 2 for V-Sequence 4
HBLK Toggle Position 3 for V-Sequence 4
HBLK Toggle Position 4 for V-Sequence 4
HBLK Toggle Position 5 for V-Sequence 4
HBLK Toggle Position 6 for V-Sequence 4
CLPOB Toggle Position 1 for V-Sequence 4
CLPOB Toggle Position 2 for V-Sequence 4
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
A1
A2
A3
A4
A5
A6
A7
REV. 0
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