參數(shù)資料
型號(hào)： AD9985KSTZ-110
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/32頁(yè)
文件大小： 0K
描述： IC INTERFACE 8BIT 110MSPS 80LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 視頻
接口： 串行
電源電壓： 2.2 V ~ 3.45 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
AD9985
Rev. 0 | Page 15 of 32
Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
AD9985KSTZ
AD9985BSTZ
Standard
Modes
Resolution
Refresh
Rate (Hz)
Horizontal
Frequency (kHz)
Pixel Rate
(MHz)
PLL
Div
VCORNGE
Current
VCORNGE
Current
VGA
640 × 480
60
31.5
25.175
799
00
110
00
011
72
37.7
31.500
835
00
110
01
010
75
37.5
31.500
841
00
110
01
010
85
43.3
36.000
831
01
100
01
010
SVGA
800 × 600
56
35.1
36.000
1025
01
100
01
010
60
37.9
40.000
1055
01
100
01
011
72
48.1
50.000
1039
01
101
01
100
75
46.9
49.500
1055
01
101
01
100
85
53.7
56.250
1047
01
101
01
101
XGA
1024 × 768
60
48.4
65.000
1343
10
101
10
011
70
56.5
75.000
1327
10
100
10
011
75
60.0
78.750
1313
10
100
10
011
80
64.0
85.500
1335
10
101
10
100
85
68.3
94.500
1383
10
101
10
100
SXGA
1280 × 1024
60
64.0
108.000
1687
10
110
10
101
75
80.0
135.000
1687
11
110
TV Modes
480i
720 × 480
60
15.75
13.51
857
00
011
00
011
480p
720 × 483
60
31.47
27.00
857
00
110
00
011
720p
1280 × 720
60
45.0
74.25
1649
10
100
10
011
1080i
1920 × 1080
60
33.75
74.25
2199
10
100
10
011
TIMING
The following timing diagrams show the operation of the
AD9985.
The output data clock signal is created so that its rising edge
always occurs between data transitions and can be used to latch
the output data externally.
There is a pipeline in the AD9985, which must be flushed before
valid data becomes available. This means that four data sets are
presented before valid data is available.
tPER
tCYCLE
tSKEW
DATACK
DATA
HSOUT
04799-0-009
Figure 9. Output Timing
HSYNC TIMING
Horizontal Sync (Hsync) is processed in the AD9985 to
eliminate ambiguity in the timing of the leading edge with
respect to the phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with
respect to Hsync, through a full 360° in 32 steps via the phase
adjust register (to optimize the pixel sampling time). Display
systems use Hsync to align memory and display write cycles, so
it is important to have a stable timing relationship between
Hsync output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9985. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be
programmed either active high or active low (Register 0EH,
Bit 5). Second, HSOUT is aligned with DATACK and data
outputs. Third, the duration of HSOUT (in pixel clocks) is set
via Register 07H. HSOUT is the sync signal that should be used
to drive the rest of the display system.
COAST TIMING
In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary and should not be used, and
the pin should be permanently connected to the inactive state.
In some systems, however, Hsync is disturbed during the
Vertical Sync period (Vsync). In some cases, Hsync pulses
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