參數(shù)資料
型號(hào): AD9985AKSTZ-140
廠商: ANALOG DEVICES INC
元件分類: 其它接口
英文描述: 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
中文描述: SPECIALTY INTERFACE CIRCUIT, PQFP80
封裝: LEAD FREE, MS-026-BEC, PLASTIC, LQFP-80
文件頁數(shù): 25/32頁
文件大小: 344K
代理商: AD9985AKSTZ-140
AD9985A
Table 38. Detected Coast Input Polarity Status
Polarity Status
0
1
Rev. 0 | Page 25 of 32
Result
Coast polarity negative
Coast polarity positive
This indicates that Bit 1 of Register 5 is the 4:2:2
output mode select bit.
1
4:2:2 Output Mode Select
A bit that configures the output data in 4:2:2 mode.
This mode can be used to reduce the number of data
lines used from 24 down to 16 for applications using
YUV, YCbCr, or YPbPr graphics signals. A timing
diagram for this mode is shown in Figure 11.
15
Recommended input and output configurations are
shown in Table 39 and Table 40.
Table 39. 4:2:2 Output Mode Select
Select
0
1
Output Mode
4:2:2
4:4:4
Table 40. 4:2:2 Input/Output Configuration
Channel
Input Connection
Red
V
Green
Y
Blue
U
Output Format
U/V
Y
High impedance
16
7
Extra PLL Divider
A bit that can add an additional divide-by-2 into the
PLL divide ratio. Enabling this function at pixel
frequencies below 20 MHz can result in improved PLL
jitter performance, as it allows the VCO to run at a
higher frequency, resulting in lower jitter.
Table 41. PLL VCO Divide
Select
PLL Divider
0
Off
1
Extra divide-by-2
16
6-5
Two bits that can control the bandwidth of the sync-
on-green input (SOGIN). In most applications, the
SOGIN bandwidth should be set to its maximum
(300 MHz). When there is excessive noise on SOGIN,
reducing the bandwidth can help suppress the noise.
SOGIN Bandwidth
Table 42. SOGIN Bandwidth
Select
00
01 or 10
11
Pulses Filtered
300 MHz
13 MHz
6.5 MHz
16
4
This bit controls the bandwidth of the red, green,
and blue analog inputs. In most applications, the
analog input bandwidth should be set to its maximum
(300 MHz). When there is excessive noise on the
analog inputs, reducing the bandwidth can help
suppress the noise.
Table 43. Anti-Aliasing Filter
Select
Input Bandwidth
0
300 MHz
1
7 MHz
Analog Input Bandwidth
19
7:0
Red Target Code
This specifies the targeted value of the final offset
for the red channel when auto-offset is used
(Register 0x1D, Bit 7 = 1). Default is 4.
1A
7:0
Green Target Code
This specifies the targeted value of the final offset
for the green channel when auto-offset is used
(Register 0x1D Bit 7 = 1). Default is 4.
1B
7:0
Blue Target Code
This specifies the targeted value of the final offset
for the blue channel when auto-offset is used
(Register 0x1D, Bit 7 = 1). Default is 4.
1D
7
Auto-Offset Enable
Enables the auto-offset circuitry. Default is 0.
1D
6
Hold Auto-Offset
Holds the offset output of the auto-offset at the
current value. Default is 0.
1D
1:0
Update Mode
Changes the update rate of the auto-offset.
Default is 10.
Table 44. Auto-Offset Update Rate
Update Mode
Auto-Offset Update Timing
00
01
10
Every clamp cycle
Every 16 clamp cycles
Every 64 camp cycles
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