- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373972 > AD9985ABSTZ-110 (ANALOG DEVICES INC) 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays PDF資料下載
參數(shù)資料
| 型號： | AD9985ABSTZ-110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP80 |
| 封裝： | LEAD FREE, MS-026-BEC, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大小： | 344K |
| 代理商： | AD9985ABSTZ-110 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD9985A
black output (code 0x00) when the known black input is
present. The offset then remains in place when other signal
levels are processed, and the entire signal is shifted to eliminate
offset errors.
Rev. 0 | Page 12 of 32
In most PC graphics systems, black is transmitted between
active video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace), and a black signal is provided
to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is virtually
always a period following Hsync, called the back porch, when a
good black reference is provided. This is the time when clamp-
ing should be performed.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time (with External Clamp = 1).
The polarity of this signal is set by the clamp polarity bit.
A simpler method of clamp timing uses the AD9985A internal
clamp timing generator. The clamp placement register is pro-
grammed with the number of pixel times that should pass after
the trailing edge of Hsync before clamping starts. A second
register (clamp duration) sets the duration of the clamp. These
are both 8-bit values, which provide considerable flexibility in
clamp generation. The clamp timing is referenced to the trailing
edge of Hsync because, though Hsync duration can vary widely,
the back porch (black reference) always follows Hsync. A good
starting point for establishing clamping is to set the clamp
placement to 0x09 (providing 9 pixel periods for the graphics
signal to stabilize after sync) and set the clamp duration to 0x14
(giving the clamp 20 pixel periods to re-establish the black
reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this
capacitor affects the performance of the clamp. If it is too small,
there is a significant amplitude change during a horizontal line
time (between clamping intervals). If the capacitor is too large,
it takes excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within 1/2 LSB in 10 lines with a clamp duration of 20 pixel
periods on a 60 Hz SXGA signal.
YUV Clamping
YUV graphics signals are slightly different from RGB signals, as
the dc reference level (black level in RGB signals) can be at the
midpoint of the graphics signal rather than at the bottom. For
these signals, it might be necessary to clamp to the midscale
range of the ADC range (0x80) rather than at the bottom of the
ADC converter range (0x00).
Clamping to midscale rather than to ground can be accom-
plished by setting the clamp select bits in the serial bus register.
Each of the three converters has its own selection bit so that
they can be clamped to either midscale or ground independ-
ently. These bits are located in Register 0x10, Bits [2:0]. The
midscale reference voltage that each ADC clamps to is provided
on the MIDSCV pin (Pin 37). This pin should be bypassed to
ground with a 0.1 μF capacitor, even if midscale clamping is not
required.
GAIN AND OFFSET CONTROL
The AD9985A can accommodate input signals with inputs
ranging from 0.5 V to 1.0 V full scale. The full-scale range is set
in three 8-bit registers (red gain, green gain, and blue gain).
Note that increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (red offset,
green offset, blue offset) provide independent settings for each
channel. The offset controls provide a ±63 LSB adjustment
range. This range is connected with the full-scale range, so if the
input range is doubled (from 0.5 V to 1.0 V), the offset step size
is also doubled (from 2 mV per step to 4 mV per step).
Figure 4 shows the interaction of gain and offset controls. The
magnitude of an LSB in offset adjustment is proportional to the
full-scale range, so changing the full-scale range also changes
the offset. The change is minimal if the offset setting is near
midscale. When changing the offset, the full-scale range is not
affected, but the full-scale level is shifted by the same amount as
the zero-scale level.
GAIN
1.0
0
00H
FFH
I
0.5
OFFSET = 00H
OFFSET = 3FH
OFFSET = 7FH
OFFSET = 00H
OFFSET = 7FH
OFFSET = 3FH
0
Figure 4. Gain and Offset Control
Auto Offset
In addition to the manual offset adjustment mode (via registers
0x0B to 0x0D), the AD9985A also includes circuitry to auto-
matically calibrate the offset for each channel. By monitoring
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9985AKSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985AKSTZ-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985BSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985KSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9985AKSTZ-110 | 功能描述:IC INTERFACE 8BIT 110MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9985AKSTZ-140 | 功能描述:IC INTERFACE 8BIT 140MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9985BST-110 | 制造商:Analog Devices 功能描述:110 MSPS/140 MSPS ANLG INTRFC FOR FLAT PNL DISPLAYS 80LQFP - Bulk |
| AD9985BSTZ-110 | 功能描述:IC INTERFACE 8BIT 110MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9985KST-110 | 制造商:Analog Devices 功能描述:110 MSPS/140 MSPS ANLG INTRFC FOR FLAT PNL DISPLAYS 80LQFP - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。