參數(shù)資料
型號: AD9985
廠商: Analog Devices, Inc.
英文描述: 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
中文描述: 110 MSPS/140 MSPS的模擬接口的平板顯示器
文件頁數(shù): 8/32頁
文件大小: 349K
代理商: AD9985
AD9985
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 8 of 32
0
80 79 78 77 76
71 70 69 68
75 74 73 72
21 22 23 24 25 26 27 28 29 30 31 32 33
1
2
3
4
5
6
7
8
9
10
11
13
12
60
59
58
57
56
55
54
53
52
51
50
49
48
AD9985
TOP VIEW
(Not to Scale)
G
V
D
V
D
G
G
P
D
P
D
G
C
H
V
G
F
G
V
D
V
D
R
R
R
R
R
R
R
R
V
D
G
GND
GREEN <7>
GREEN <6>
GREEN <5>
GREEN <4>
GREEN <3>
GREEN <2>
GREEN <1>
GREEN <0>
GND
V
DD
BLUE <7>
BLUE <6>
BLUE <5>
BLUE <4>
BLUE <3>
BLUE <2>
BLUE <1>
BLUE <0>
GND
V
D
REF BYPASS
SDA
SCL
A0
R
AIN
GND
V
D
V
D
GND
SOGIN
G
AIN
GND
V
D
V
D
GND
B
AIN
V
D
GND
PIN 1
14
15
16
17
18
20
19
47
46
45
44
43
42
41
GND
64 63 62 61
67 66 65
34 35 36 37 38 39 40
P
D
P
D
G
M
C
V
D
G
D
H
S
V
G
V
D
G
Figure 2. Pin Configuration
Table 4. Complete Pinout List
Pin Type
Inputs
Outputs
References
Mnemonic
R
AIN
G
AIN
B
AIN
HSYNC
VSYNC
SOGIN
CLAMP
COAST
Red [7:0]
Green [7:0]
Blue [7:0]
DATACK
HSOUT
VSOUT
SOGOUT
REF BYPASS
MIDSCV
Function
Analog Input for Converter R
Analog Input for Converter G
Analog Input for Converter B
Horizontal SYNC Input
Vertical SYNC Input
Input for Sync-on-Green
Clamp Input (External CLAMP Signal)
PLL COAST Signal Input
Outputs of Converter Red, Bit 7 is the MSB
Outputs of Converter Green, Bit 7 is the BSB
Outputs of Converter Blue, Bit 7 is the BSB
Data Output Clock
HSYNC Output (Phase-Aligned with DATACK)
VSYNC Output (Phase-Aligned with DATACK)
Sync-on-Green Slicer Output
Internal Reference Bypass
Internal Midscale Voltage Bypass
Connection for External Filter Components
for Internal PLL
Analog Power Supply
Output Power Supply
PLL Power Supply
Ground
Value
0.0 V to 1.0V
0.0 V to 1.0V
0.0 V to 1.0V
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
1.25 V
Pin No.
54
48
43
30
31
49
38
29
70–77
2–9
12–19
67
66
64
65
58
37
Power Supply
FILT
V
D
V
DD
PV
D
GND
3.3 V
3.3 V
3.3 V
0 V
33
39, 42, 45, 46, 51, 52, 59, 62
11, 22, 23, 69, 78, 79
26, 27, 34, 35
1, 10, 20, 21, 24, 25, 28, 32, 36, 40, 41,
44, 47, 50, 53, 60, 61, 63, 68, 80
57
56
55
Control
SDA
SCL
A0
Serial Port Data I/O
Serial Port Data Clock (100 kHz Maximum
Serial Port Address Input 1
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
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