參數(shù)資料
型號(hào): AD9984AKSTZ-170
廠商: ANALOG DEVICES INC
元件分類: 其它接口
英文描述: High Performance 10-Bit Display Interface
中文描述: SPECIALTY INTERFACE CIRCUIT, PQFP80
封裝: ROHS COMPLIANT, MS-026BEC, LQFP-80
文件頁(yè)數(shù): 31/44頁(yè)
文件大?。?/td> 490K
代理商: AD9984AKSTZ-170
AD9984A
0x05—Bits[6:0] Red Channel Gain Control MSBs
This register contains the 7-bit MSBs of the red channel gain
control. Values written to this register are not updated until the
LSB register (Register 0x06) has also been written to. The
power-up default is 1000000.
0x06 —Bits[7:6] Red Channel Gain Control LSBs
This register contains the 2-bit LSBs of the red channel gain
control. Along with the 7 MSBs of gain control in Register 0x05,
there are 9 bits of gain control. Default power-up value is 00.
0x07—Bits[6:0] Green Channel Gain Control MSBs
This register contains the 7-bit MSBs of the green channel gain
control. Register update requires writing 0x00 to Register 0x08.
0x08—Bits[7:6] Green Channel Gain Control LSBs
This register contains the 2-bit LSBs of the green channel gain
control. Along with the 7 MSBs of gain control in Register 0x07,
there are 9 bits of gain control. Default power-up value is 00.
0x09—Bits[6:0] Blue Channel Gain Control MSBs
This register contains the 7-bit MSBs of the blue channel gain
control. Register update requires writing 0x00 to Register 0x0A.
0x0A—Bits[7:6] Blue Channel Gain Control LSBs
This register contains the 2-bit LSBs of the blue channel gain
control. Along with the 7 MSBs of gain control in Register 0x09,
there are 9 bits of gain control. Default power-up value is 00.
INPUT OFFSET
The offset control shifts the analog input, resulting in a change
in brightness. Note that the function of the red, blue, or green
channel offset registers depends on whether auto-offset is
enabled (Register 0x1B, Bit 5).
If auto-offset is disabled, nine bits of the offset registers
(Bits[6:0] of the offset MSB register plus Bits[7:6] of the following
register) control the absolute offset added to the channel (for
the red channel, Register 0x0B, Bits[6:0] plus Register 0x0C,
Bits[7:6]) control the absolute offset added to the channel. The
offset control provides a ±255 LSBs of adjustment range, with
1 LSB of offset corresponding to 1 LSB of output code.
If auto-offset is enabled, the 11-bit offset (comprised of the
8 bits of the MSB register and Bits[7:5] of the following LSB
register) determines the clamp target code. The 11-bit offset
consists of 1 sign bit plus 10 bits. If the register is programmed to
530d, the output code is equal to 530d at the end of the clamp
period. Note that incrementing the offset register setting by
1 LSB adds 1 LSB of offset, regardless of the auto-offset setting.
0x0B—Bits[7:0] Red Channel Offset Control MSBs
This register is the 8-bit MSBs of the red channel offset control.
Along with the 3 LSBs in the red channel offset in Register 0x0C,
there are 11 bits of dc offset control in the red channel. Values
written to this register are not updated until the LSB register
(Register 0x0C) has also been written to.
Rev. 0 | Page 31 of 44
0x0C—Bits[7:5] Red Channel Offset Control LSBs
This register contains the 3-bit LSBs of the red channel offset
control. Combining these bits with the 8 bits of MSBs in
Register 0x0B creates 11 bits of offset control.
0x0D—Bits[7:0] Green Channel Offset Control MSBs
This register contains the 8-bit MSBs of the green channel offset
control. Update of this register occurs only when Register 0x0E
is also written to.
0x0E—Bits[7:5] Green Channel Offset Control LSBs
This register contains the 3-bit LSBs of the green channel offset
control. Combining these bits with the 8 bits of MSBs in the
Register 0x0D makes 11 bits of offset control.
0x0F—Bits[7:0] Blue Channel Offset Control MSBs
The 8-bit blue channel offset control. Update of this register
occurs only when Register 0x10 is also written to.
0x10—Bits[7:5] Blue Channel Offset Control LSBs
The LSBs of the blue channel offset control combine with the
8 bits of MSBs in the Register 0x0F to make 11 bits of offset control.
HSYNC CONTROL
0x11—Bits[7:0] Sync Separator Threshold
This register sets the threshold of the sync separator’s digital
comparator. The value written to this register is multiplied by
200 ns to get the threshold value. Therefore, if a value of 5 is
written, the digital comparator threshold is 1 μs and any pulses
less than 1 μs are rejected by the sync separator. There is some
variability to the 200 ns multiplier value. The maximum
variability over all operating conditions is ±20% (160 ns to
240 ns). Because normal Vsync and Hsync pulse widths differ
by a factor of about 500 or more, the 20% variability is not an
issue. The power-up default value is 32d.
0x12—Bit[7] Hsync Source Override
This bit is the Hsync source override. Setting this bit to 0 allows
the chip to determine the active Hsync source. Setting it to 1
uses Bit 6 of Register 0x12 to determine the active Hsync
source. Power-up default value is 0.
Table 18. Hsync Source Override Bit
Value
Result
0
Hsync source determined by chip.
1
Hsync source determined by user (Register 0x12, Bit 6).
0x12—Bit[6] Hsync Source Select
This bit selects the source of the Hsync for PLL and sync processing
(only if Bit 7 of Register 0x12 is set to 1 or if both syncs are active).
Setting this bit to 0 specifies the Hsync from the input pin.
Setting it to 1 selects Hsync from SOG. Power-up default is 0.
Table 19. Hsync Source Select Bit
Value
Result
0
HSYNCx input.
1
Hsync from SOG.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9984APCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 10-Bit Display Interface
AD9984KSTZ-110 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
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AD9984KSTZ-170 制造商:Analog Devices 功能描述:
AD9985 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS/140 MSPS Analog Interface for Flat Panel Displays