參數(shù)資料
型號(hào)： AD9984AKSTZ-140
廠商： Analog Devices Inc
文件頁數(shù)： 17/44頁
文件大?。?/td> 0K
描述： IC DISPLAY 10BIT 140MSPS 80LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 接口
應(yīng)用： 顯示器，處理，電視
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
AD9984A
Rev. 0 | Page 24 of 44
2-WIRE SERIAL REGISTER MAP
The AD9984A is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to
write and read the control registers through the 2-wire serial interface port.
Table 14. Control Register Map
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
0x00
RO
7:0
0010 0000
Chip Revision
An 8-bit register that represents the silicon revision level.
0x01
R/W
7:0
0110 1001
PLL Div MSBs
The 8 MSBs (Bits[11:4] of the PLL Divider. Larger values mean the PLL
operates at a faster rate. This register should be loaded first when a
change is needed. (This gives the PLL more time to lock).1
0x02
R/W
7:4
1101 ****
PLL Div LSBs
The 4 LSBs (Bits[3:0]) of the PLL Divider. Links to the PLL Div MSB to
make a 12-bit register.1
0x03
R/W
7:6
01** ****
VCO/CPMP
VCO Range Select. Chooses the VCO frequency range (see the Clock
Generation section).
5:3
**00 1***
Charge Pump Current. Varies the current that drives the low-pass filter
(see the Clock Generation section).
2
**** *0**
External Clock Enable.
0x04
R/W
7:3
1000 0***
Phase Adjust
ADC Clock Phase Adjust. Larger values mean more delay. (1 LSB = T/32).
0x05
R/W
6:0
*100 0000
Red Gain MSBs
The 7 MSBs of the Red Channel Gain Control. Controls ADC input range
(contrast) of each respective channel. Larger values give less contrast.
0x06
R/W
7:6
00** ****
Red Gain LSBs
The 2 LSBs of the Red Channel Gain Control. Links with Register 0x05
to form the 9-bit red gain that controls the ADC input range (contrast)
of the red channel. A lower value corresponds to a higher gain.1
0x07
R/W
6:0
*100 0000
Green Gain MSBs
The 7 MSBs of the Green Channel Gain Control. Controls ADC input
range (contrast) of each respective channel. Larger values give less
contrast.
0x08
R/W
7:6
00** ****
Green Gain LSBs
The 2 LSBs of the Green Channel Gain Control. Links to Register 0x07
to form the 9-bit green gain that controls the ADC input range (contrast)
of the green channel. A lower value corresponds to a higher gain.1
0x09
R/W
6:0
*100 0000
Blue Gain MSBs
The 7 MSBs of the Blue Channel Gain Control. Controls ADC input range
(contrast) of each respective channel. Larger values give less contrast.
0x0A
R/W
7:6
00** ****
Blue Gain LSBs
The 2 LSBs of the Blue Channel Gain Control. Links to Register 0x09
to form the 9-bit blue gain that controls the ADC input range (contrast)
of the blue channel. A lower value corresponds to a higher gain.1
0x0B
R/W
7:0
0100 0000
Red Offset MSBs
The 8 MSBs of the Red Channel Offset Control. Controls dc offset
(brightness) of each respective channel. Larger values decrease
brightness.1
0x0C
R/W
7:5
000* ****
Red Offset LSBs
The 3 LSBs of the Red Channel Offset Control. Links to Register 0x0B
to form the 11-bit red offset that controls the dc offset (brightness)
of the red channel in auto-offset mode.
0x0D
R/W
7:0
0100 0000
Green Offset MSBs
The 8 MSBs of the Green Channel Offset Control. Controls dc offset
(brightness) of each respective channel. Larger values decrease
brightness.1
0x0E
R/W
7:5
000* ****
Green Offset LSBs
The 3 LSBs of the Green Channel Offset Control. Links to Register 0x0D
to form the 11-bit green offset that controls the dc offset (brightness)
of the green channel in auto-offset mode.
0x0F
R/W
7:0
0100 0000
Blue Offset MSBs
The 8 MSBs of the Blue Channel Offset Control. Controls dc offset
(brightness) of each respective channel. Larger values decrease
brightness.1
0x10
R/W
7:5
000* ****
Blue Offset LSBs
The 3 LSBs of the Blue Channel Offset Control. Links to Register 0x0F
to form the 11-bit blue offset that controls the dc offset (brightness)
of the blue channel in auto-offset mode.
0x11
R/W
7:0
0010 0000
Sync Separator
Threshold
Sets the threshold of the sync separator’s digital comparator.
0x12
R/W
7
0*** ****
Hsync Control
Hsync Source Override.
0 = The chip determines the active Hsync source.
1 = The active Hsync source is set by Reg. 0x12, Bit 6.
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